Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp2458237imu; Mon, 19 Nov 2018 00:28:51 -0800 (PST) X-Google-Smtp-Source: AJdET5cbXgDAC+SZpCmklg29nkNUMTfbxFtX1Mko/auklh1UE1LvhVKSp46qx+5+9ddNzM/In8zg X-Received: by 2002:a63:4815:: with SMTP id v21mr19144728pga.308.1542616131692; Mon, 19 Nov 2018 00:28:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542616131; cv=none; d=google.com; s=arc-20160816; b=cInGs/xx2oVN03b9yu3Jg3qmYMZ15/vGovYILeO39jnqDtnR+MVzS6eDu9GtzXZ05K 71bXorqHY6FYs8T4PIYU6FyTWJMXNB+6ro5ZhgAC5vqKJFJiWZcmpFlsRytCdASlJkMG P5FWta65rOMJTDg/j+hB2SnPQh8xy+Tbj9kYf/tUff8An5kPWnNFL2OfwMGEqj9T4R3N z4lZyQ5ygjPHb1jOh/UMtkKMvgvHL9yhMJdlQ3J1MHEybAJf0+Pj8G0ee3VsLhfVmGEk gmiFdPaEBErf2gA/VuAbPvQsIRLEE5UTXMo2gkod0R+JG1qQ0rYSXbflg4uzHiPlzMSj 2zcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:subject:cc:to:from:date; bh=BMPsJ33Gs3adrVV+hHOnoMPdylghZdoWknvdwP7EY44=; b=Y49bitH94QUbNkmJbsd+9eAb1r2e2MUyK3/FXwmNnlmFbAXUQ68f7NljBTkEPQJBqr yn7UWIlLzaDHioYwMvLR0xOPEO4VEINEnZivvMwZ8dqL9YORX4gnQQzMpls9mCqsja5d 2+k/wA22bPlBNhEb0egsEKo9YSoerSzHG8J2UYvZVHQMUc8d3u9dXrHYhgNB9JniZ8Dx 9yQJ39cPjYMKRLoCamNfX4rn0O4BDwCmAhqI2CS6HC7qJf7yl1NzoF6MFG7wqcl9lLYW I+BBbd97Dm8ONTs+pdOGt7Nl9x/3F7rEBlZBtdSDNn+/eq18PPtlFIEIU3cy03YT/kRk rVVA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e31si36029528pge.270.2018.11.19.00.28.36; Mon, 19 Nov 2018 00:28:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727097AbeKSSta (ORCPT + 99 others); Mon, 19 Nov 2018 13:49:30 -0500 Received: from mail.bootlin.com ([62.4.15.54]:36876 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726175AbeKSSta (ORCPT ); Mon, 19 Nov 2018 13:49:30 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 4B37E20CFD; Mon, 19 Nov 2018 09:26:33 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.2 Received: from bootlin.com (aaubervilliers-681-1-13-146.w90-88.abo.wanadoo.fr [90.88.134.146]) by mail.bootlin.com (Postfix) with ESMTPSA id C9C6F2039F; Mon, 19 Nov 2018 09:26:32 +0100 (CET) Date: Mon, 19 Nov 2018 09:26:32 +0100 From: Maxime Chevallier To: Grygorii Strashko Cc: "David S. Miller" , Kishon Vijay Abraham I , Russell King - ARM Linux , , Sekhar Nori , , , Tony Lindgren , , , Alexandre Belloni , Antoine Tenart , Quentin Schulz , Vivek Gautam , Maxime Ripard , Chen-Yu Tsai , Carlo Caione , Chunfeng Yun , Matthias Brugger , Manu Gautam Subject: Re: [PATCH v2 4/5] phy: mvebu-cp110-comphy: convert to use eth phy mode and submode Message-ID: <20181119092632.7048bc46@bootlin.com> In-Reply-To: <20181109234755.21687-5-grygorii.strashko@ti.com> References: <20181109234755.21687-1-grygorii.strashko@ti.com> <20181109234755.21687-5-grygorii.strashko@ti.com> X-Mailer: Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Grygorii, On Fri, 9 Nov 2018 17:47:54 -0600 Grygorii Strashko wrote: >Convert mvebu-cp110-comphy PHY driver to use recently introduced >PHY_MODE_ETHERNET and phy_set_mode_ext(). Sorry I missed your V2, hopefully I tested the right version this time. Tested on MCBin, this works just fine. Thanks, Tested-by: Maxime Chevallier >Signed-off-by: Grygorii Strashko >--- > drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 19 +----- > drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 83 ++++++++++++++----------- > 2 files changed, 48 insertions(+), 54 deletions(-) > >diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c >index 7a37a37..731793a 100644 >--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c >+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c >@@ -1165,28 +1165,13 @@ static void mvpp22_gop_setup_irq(struct mvpp2_port *port) > */ > static int mvpp22_comphy_init(struct mvpp2_port *port) > { >- enum phy_mode mode; > int ret; > > if (!port->comphy) > return 0; > >- switch (port->phy_interface) { >- case PHY_INTERFACE_MODE_SGMII: >- case PHY_INTERFACE_MODE_1000BASEX: >- mode = PHY_MODE_SGMII; >- break; >- case PHY_INTERFACE_MODE_2500BASEX: >- mode = PHY_MODE_2500SGMII; >- break; >- case PHY_INTERFACE_MODE_10GKR: >- mode = PHY_MODE_10GKR; >- break; >- default: >- return -EINVAL; >- } >- >- ret = phy_set_mode(port->comphy, mode); >+ ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET, >+ port->phy_interface); > if (ret) > return ret; > >diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c >index 79b52c3..7dee72b 100644 >--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c >+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c >@@ -9,6 +9,7 @@ > #include > #include > #include >+#include > #include > #include > #include >@@ -131,26 +132,26 @@ struct mvebu_comhy_conf { > > static const struct mvebu_comhy_conf mvebu_comphy_cp110_modes[] = { > /* lane 0 */ >- MVEBU_COMPHY_CONF(0, 1, PHY_MODE_SGMII, 0x1), >- MVEBU_COMPHY_CONF(0, 1, PHY_MODE_2500SGMII, 0x1), >+ MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1), >+ MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1), > /* lane 1 */ >- MVEBU_COMPHY_CONF(1, 2, PHY_MODE_SGMII, 0x1), >- MVEBU_COMPHY_CONF(1, 2, PHY_MODE_2500SGMII, 0x1), >+ MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1), >+ MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1), > /* lane 2 */ >- MVEBU_COMPHY_CONF(2, 0, PHY_MODE_SGMII, 0x1), >- MVEBU_COMPHY_CONF(2, 0, PHY_MODE_2500SGMII, 0x1), >- MVEBU_COMPHY_CONF(2, 0, PHY_MODE_10GKR, 0x1), >+ MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1), >+ MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1), >+ MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1), > /* lane 3 */ >- MVEBU_COMPHY_CONF(3, 1, PHY_MODE_SGMII, 0x2), >- MVEBU_COMPHY_CONF(3, 1, PHY_MODE_2500SGMII, 0x2), >+ MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2), >+ MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2), > /* lane 4 */ >- MVEBU_COMPHY_CONF(4, 0, PHY_MODE_SGMII, 0x2), >- MVEBU_COMPHY_CONF(4, 0, PHY_MODE_2500SGMII, 0x2), >- MVEBU_COMPHY_CONF(4, 0, PHY_MODE_10GKR, 0x2), >- MVEBU_COMPHY_CONF(4, 1, PHY_MODE_SGMII, 0x1), >+ MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2), >+ MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2), >+ MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2), >+ MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1), > /* lane 5 */ >- MVEBU_COMPHY_CONF(5, 2, PHY_MODE_SGMII, 0x1), >- MVEBU_COMPHY_CONF(5, 2, PHY_MODE_2500SGMII, 0x1), >+ MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1), >+ MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1), > }; > > struct mvebu_comphy_priv { >@@ -163,10 +164,12 @@ struct mvebu_comphy_lane { > struct mvebu_comphy_priv *priv; > unsigned id; > enum phy_mode mode; >+ int submode; > int port; > }; > >-static int mvebu_comphy_get_mux(int lane, int port, enum phy_mode mode) >+static int mvebu_comphy_get_mux(int lane, int port, >+ enum phy_mode mode, int submode) > { > int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes); > >@@ -177,7 +180,7 @@ static int mvebu_comphy_get_mux(int lane, int port, enum phy_mode mode) > for (i = 0; i < n; i++) { > if (mvebu_comphy_cp110_modes[i].lane == lane && > mvebu_comphy_cp110_modes[i].port == port && >- mvebu_comphy_cp110_modes[i].mode == mode) >+ mvebu_comphy_cp110_modes[i].mode == submode) > break; > } > >@@ -187,8 +190,7 @@ static int mvebu_comphy_get_mux(int lane, int port, enum phy_mode mode) > return mvebu_comphy_cp110_modes[i].mux; > } > >-static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane, >- enum phy_mode mode) >+static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane) > { > struct mvebu_comphy_priv *priv = lane->priv; > u32 val; >@@ -206,14 +208,14 @@ static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane, > MVEBU_COMPHY_SERDES_CFG0_HALF_BUS | > MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xf) | > MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xf)); >- if (mode == PHY_MODE_10GKR) >+ if (lane->submode == PHY_INTERFACE_MODE_10GKR) > val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) | > MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe); >- else if (mode == PHY_MODE_2500SGMII) >+ else if (lane->submode == PHY_INTERFACE_MODE_2500BASEX) > val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x8) | > MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x8) | > MVEBU_COMPHY_SERDES_CFG0_HALF_BUS; >- else if (mode == PHY_MODE_SGMII) >+ else if (lane->submode == PHY_INTERFACE_MODE_SGMII) > val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) | > MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x6) | > MVEBU_COMPHY_SERDES_CFG0_HALF_BUS; >@@ -243,7 +245,7 @@ static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane, > /* refclk selection */ > val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); > val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL; >- if (mode == PHY_MODE_10GKR) >+ if (lane->submode == PHY_INTERFACE_MODE_10GKR) > val |= MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE; > writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); > >@@ -261,8 +263,7 @@ static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane, > writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); > } > >-static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane, >- enum phy_mode mode) >+static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane) > { > struct mvebu_comphy_priv *priv = lane->priv; > u32 val; >@@ -303,13 +304,13 @@ static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane, > return 0; > } > >-static int mvebu_comphy_set_mode_sgmii(struct phy *phy, enum phy_mode mode) >+static int mvebu_comphy_set_mode_sgmii(struct phy *phy) > { > struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); > struct mvebu_comphy_priv *priv = lane->priv; > u32 val; > >- mvebu_comphy_ethernet_init_reset(lane, mode); >+ mvebu_comphy_ethernet_init_reset(lane); > > val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); > val &= ~MVEBU_COMPHY_RX_CTRL1_CLK8T_EN; >@@ -330,7 +331,7 @@ static int mvebu_comphy_set_mode_sgmii(struct phy *phy, enum phy_mode mode) > val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0x1); > writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); > >- return mvebu_comphy_init_plls(lane, PHY_MODE_SGMII); >+ return mvebu_comphy_init_plls(lane); > } > > static int mvebu_comphy_set_mode_10gkr(struct phy *phy) >@@ -339,7 +340,7 @@ static int mvebu_comphy_set_mode_10gkr(struct phy *phy) > struct mvebu_comphy_priv *priv = lane->priv; > u32 val; > >- mvebu_comphy_ethernet_init_reset(lane, PHY_MODE_10GKR); >+ mvebu_comphy_ethernet_init_reset(lane); > > val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); > val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL | >@@ -469,7 +470,7 @@ static int mvebu_comphy_set_mode_10gkr(struct phy *phy) > val |= MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1a); > writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); > >- return mvebu_comphy_init_plls(lane, PHY_MODE_10GKR); >+ return mvebu_comphy_init_plls(lane); > } > > static int mvebu_comphy_power_on(struct phy *phy) >@@ -479,7 +480,8 @@ static int mvebu_comphy_power_on(struct phy *phy) > int ret, mux; > u32 val; > >- mux = mvebu_comphy_get_mux(lane->id, lane->port, lane->mode); >+ mux = mvebu_comphy_get_mux(lane->id, lane->port, >+ lane->mode, lane->submode); > if (mux < 0) > return -ENOTSUPP; > >@@ -492,12 +494,12 @@ static int mvebu_comphy_power_on(struct phy *phy) > val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id); > regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val); > >- switch (lane->mode) { >- case PHY_MODE_SGMII: >- case PHY_MODE_2500SGMII: >- ret = mvebu_comphy_set_mode_sgmii(phy, lane->mode); >+ switch (lane->submode) { >+ case PHY_INTERFACE_MODE_SGMII: >+ case PHY_INTERFACE_MODE_2500BASEX: >+ ret = mvebu_comphy_set_mode_sgmii(phy); > break; >- case PHY_MODE_10GKR: >+ case PHY_INTERFACE_MODE_10GKR: > ret = mvebu_comphy_set_mode_10gkr(phy); > break; > default: >@@ -517,10 +519,17 @@ static int mvebu_comphy_set_mode(struct phy *phy, > { > struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); > >- if (mvebu_comphy_get_mux(lane->id, lane->port, mode) < 0) >+ if (mode != PHY_MODE_ETHERNET) >+ return -EINVAL; >+ >+ if (submode == PHY_INTERFACE_MODE_1000BASEX) >+ submode = PHY_INTERFACE_MODE_SGMII; >+ >+ if (mvebu_comphy_get_mux(lane->id, lane->port, mode, submode) < 0) > return -EINVAL; > > lane->mode = mode; >+ lane->submode = submode; > return 0; > } > -- Maxime Chevallier, Bootlin Embedded Linux and kernel engineering https://bootlin.com