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[209.132.180.67]) by mx.google.com with ESMTP id q25si25375005pgv.541.2018.11.19.09.15.34; Mon, 19 Nov 2018 09:15:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2406790AbeKTDib (ORCPT + 99 others); Mon, 19 Nov 2018 22:38:31 -0500 Received: from muru.com ([72.249.23.125]:54492 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2406744AbeKTDia (ORCPT ); Mon, 19 Nov 2018 22:38:30 -0500 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id A386D80B6; Mon, 19 Nov 2018 17:14:10 +0000 (UTC) Date: Mon, 19 Nov 2018 09:14:06 -0800 From: Tony Lindgren To: Peter Ujfalusi Cc: Belisko Marek , LKML , linux-omap@vger.kernel.org, "Dr. H. Nikolaus Schaller" , Laxman Dewangan , Jon Hunter , Thierry Reding Subject: Re: omap5 fixing palmas IRQ_TYPE_NONE warning leads to gpadc timeouts Message-ID: <20181119171406.GQ53235@atomide.com> References: <20180703084516.GT112168@atomide.com> <20181113180656.GE53235@atomide.com> <46d271b2-35d3-6353-c530-3292cdac53ab@ti.com> <20181119161906.GP53235@atomide.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20181119161906.GP53235@atomide.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, * Tony Lindgren [181119 16:19]: > * Peter Ujfalusi [181119 10:16]: > > On 2018-11-13 20:06, Tony Lindgren wrote: > > > Looks like the IRQ_TYPE_NONE issue still is there for omap5 and > > > should be fixed with IRQ_TYPE_HIGH. > > > > > > No idea about why palmas interrupts would stop working though, > > > Peter, do you have any ideas on this one? > > > > No, I don't. > > The INT polarity can be changed in Palmas. > > based on the pdata->irq_flags (queried via irqd_get_trigger_type()) > > the code configures it: > > > > if (pdata->irq_flags & IRQ_TYPE_LEVEL_HIGH) > > reg = PALMAS_POLARITY_CTRL_INT_POLARITY; > > else > > reg = 0; > > > > and we pass the same irq_flags to the regmap_add_irq_chip() > > IRQ_TYPE_LEVEL_HIGH == IRQF_TRIGGER_HIGH == 0x00000004 > > > > A change in DT should be enough, no need to patch palmas.c, imho. > > But it's not. I'm now wondering if wakeupgen is inverting the > polarity for this interrupt? > > GIC docs say this about SPI interrupts: > > "SPI is triggered on a rising edge or is active-HIGH level-sensitive." > > So when setting IRQ_TYPE_LEVEL_HIGH in dts, we still must not > invert the polarity in palmas while tegra needs to. So either > tegra114 hardware is inverting the polarity, or omap5 wakeupgen > is. > > Does the palmas trm say which way PALMAS_POLARITY_CTRL > triggers if PALMAS_POLARITY_CTRL_INT_POLARITY is set? > > Also note that dra7 is using a gpio for palmas interrupt. Well so commit 7e9d474954f4 ("ARM: tegra: Correct polarity for Tegra114 PMIC interrupt") states that tegra114 inverts the polarity of the PMIC interrupt. So adding Jon and Thierry to Cc. So it seems that commit df545d1cd01a ("mfd: palmas: Provide irq flags through DT/platform data") wrongly sets the PALMAS_POLARITY_CTRL_INT_POLARITY on IRQ_TYPE_LEVEL_HIGH while it should set it on IRQ_TYPE_LEVEL_LOW. I think the fix needs to set the polarity using of_machine_is_compatible() and probably also add a new compatible to palmas.c for "ti,palmas-tegra114" to properly deal with the inverted interrupt. Or add a property for "interrupt-inverted". In any case, it seems that the of_machine_is_compatible() is also needed too to avoid breaking use with dtb files. Jon & Thierry, can you guys please check and confirm this? Regards, Tony