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[209.132.180.67]) by mx.google.com with ESMTP id s4-v6si47137917pfb.188.2018.11.20.00.11.57; Tue, 20 Nov 2018 00:12:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MuYhMyV9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726457AbeKTSik (ORCPT + 99 others); Tue, 20 Nov 2018 13:38:40 -0500 Received: from mail-lf1-f68.google.com ([209.85.167.68]:41875 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726346AbeKTSik (ORCPT ); Tue, 20 Nov 2018 13:38:40 -0500 Received: by mail-lf1-f68.google.com with SMTP id c16so673650lfj.8 for ; Tue, 20 Nov 2018 00:10:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=y8nfLChzKnGj3dmxM0axPkYOOwmnJ0y4626FmiTrPo0=; b=MuYhMyV9UU1QfmOzGer0nZp6DvyI6atmdcXESs9wq7xg1bqYTiV1m5l9x3Pu6XEb+a IRQO1/flovSGIYwOs38IeFs33yN4XAhYxMp52M447y3olWG6empT30Rsr1+sEfF4bLlF 7Hsrnb3rUUcydkjESRV+N1lngw4f85W34ctog= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=y8nfLChzKnGj3dmxM0axPkYOOwmnJ0y4626FmiTrPo0=; b=kounGSlGL7q0Tcl1QAiu7PxEuGdUekeWCYIuxnwBT55pbN/8Z1yj3cu5o+izo7EsQs twefpIn1ttDJD83I8okYj0yV1pZsEVGkmgzLC2TwwKgIuJYvQ4Mv2i0QYkwgzuJ4Vkbw jwM4mreGmbw9YN/5DA67Nk4N8noxg3x0Wl5cxFxqpL9YUVI/Lul0PC57rkgYVlQIGua2 FpdC+5q3iiEuQW+bSE5+P86g6aHiY0XaDrhdJQALNYGcP+OzSrKbM/dS8YEqH3IudgM0 TecaR3rXyS7koHyFZGx7cDGNPUDPbOBbWNHPaZhzGGYR3swLqSQpHHa/QvbNPXGxaZd+ 9aUQ== X-Gm-Message-State: AGRZ1gJYcs3Sd+tJx8/SrWMbZq6BrqJE/CBMiyUCjE96+S6XX6+Vj1Ex 7CcmEpbSGuHhBLcBPEd/YfqlDKrcAIeIr9UkLxA8Wg== X-Received: by 2002:a19:f813:: with SMTP id a19mr533532lff.67.1542701448664; Tue, 20 Nov 2018 00:10:48 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Linus Walleij Date: Tue, 20 Nov 2018 09:10:36 +0100 Message-ID: Subject: Re: [RFC PATCH v2 07/14] m68k: atari: Convert to clocksource API To: fthain@telegraphics.com.au Cc: Geert Uytterhoeven , schwab@linux-m68k.org, Arnd Bergmann , schivers@csc.com.au, Thomas Gleixner , Daniel Lezcano , schmitzmic@gmail.com, John Stultz , linux-m68k@lists.linux-m68k.org, "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 19, 2018 at 2:22 AM Finn Thain wrote: > Add a platform clocksource by adapting the existing arch_gettimeoffset > implementation. > > Normally the MFP timer C interrupt flag would be used to check for > timer counter wrap-around. Unfortunately, that flag gets cleared by the > MFP itself (due to automatic EOI mode). This means that > mfp_timer_c_handler() and atari_read_clk() must race when accounting > for counter wrap-around. > > That problem is avoided here by effectively stopping the clock when it > might otherwise jump backwards. This harms clock accuracy; the result > is not much better than the jiffies clocksource. Also, clock error is > no longer uniformly distributed. > > Signed-off-by: Finn Thain > Acked-by: Linus Walleij > --- > TODO: find a spare counter for the clocksource, rather than hanging > it off the HZ timer. Yes you already see the same as I see: this chip MK68901 has no less than four timers. I bet the kernel is just using one of them, out of habit. By just setting another timer as free-running we get a classic and clean Linux clocksource for the Atari. This is however a very good start in untangling the mess (as is the whole patch series). As with the Amiga, this chip also has an RTC clock that should go to the RTC subsystem, naturally. Yours, Linus Walleij