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From:   "M.h. Lian" <minghuan.lian@nxp.com>
To:     "Z.q. Hou" <zhiqiang.hou@nxp.com>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
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        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        Leo Li <leoyang.li@nxp.com>,
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        "catalin.marinas@arm.com" <catalin.marinas@arm.com>,
        "will.deacon@arm.com" <will.deacon@arm.com>
CC:     Mingkai Hu <mingkai.hu@nxp.com>, Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: RE: [PATCHv2 10/25] PCI: mobiveil: fix the INTx process error
Thread-Topic: [PATCHv2 10/25] PCI: mobiveil: fix the INTx process error
Thread-Index: AQHUgLMjYcftjmg7iE2fOoFo4PqH6KVYfyAA
Date:   Tue, 20 Nov 2018 11:00:43 +0000
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References: <20181120092615.11680-1-Zhiqiang.Hou@nxp.com>
 <20181120092615.11680-11-Zhiqiang.Hou@nxp.com>
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reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>

> -----Original Message-----
> From: Z.q. Hou
> Sent: Tuesday, November 20, 2018 5:27 PM
> To: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; lorenzo.pieralisi@arm.com;
> catalin.marinas@arm.com; will.deacon@arm.com
> Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>; Z.q. Hou
> <zhiqiang.hou@nxp.com>
> Subject: [PATCHv2 10/25] PCI: mobiveil: fix the INTx process error
>=20
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>=20
> In the loop block, there is not code change the loop key, this patch upda=
ted
> the loop key by re-read the INTx status register.
>=20
> This patch also change to clear the handled INTx status.
>=20
> Note: Need MV to test this fix.
>=20
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP dri=
ver")
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V2:
>  - Added fixes entry.
>=20
>  drivers/pci/controller/pcie-mobiveil.c | 13 +++++++++----
>  1 file changed, 9 insertions(+), 4 deletions(-)
>=20
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index 4ba458474e42..78e575e71f4d 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
>  	/* Handle INTx */
>  	if (intr_status & PAB_INTP_INTX_MASK) {
>  		shifted_status =3D csr_readl(pcie,
> PAB_INTP_AMBA_MISC_STAT);
> +		shifted_status &=3D PAB_INTP_INTX_MASK;
>  		shifted_status >>=3D PAB_INTX_START;
>  		do {
>  			for_each_set_bit(bit, &shifted_status,
> PCI_NUM_INTX) { @@ -372,12 +373,16 @@ static void
> mobiveil_pcie_isr(struct irq_desc *desc)
>  					dev_err_ratelimited(dev,
> "unexpected IRQ, INT%d\n",
>  							    bit);
>=20
> -				/* clear interrupt */
> -				csr_writel(pcie,
> -					   shifted_status << PAB_INTX_START,
> +				/* clear interrupt handled */
> +				csr_writel(pcie, 1 << (PAB_INTX_START + bit),
>  					   PAB_INTP_AMBA_MISC_STAT);
>  			}
> -		} while ((shifted_status >> PAB_INTX_START) !=3D 0);
> +
> +			shifted_status =3D csr_readl(pcie,
> +
> PAB_INTP_AMBA_MISC_STAT);
> +			shifted_status &=3D PAB_INTP_INTX_MASK;
> +			shifted_status >>=3D PAB_INTX_START;
> +		} while (shifted_status !=3D 0);
>  	}
>=20
>  	/* read extra MSI status register */
> --
> 2.17.1