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[209.132.180.67]) by mx.google.com with ESMTP id o125-v6si30586609pfb.35.2018.11.20.07.36.26; Tue, 20 Nov 2018 07:36:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=IXJzw3xL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726512AbeKUCBn (ORCPT + 99 others); Tue, 20 Nov 2018 21:01:43 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:33013 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726001AbeKUCBn (ORCPT ); Tue, 20 Nov 2018 21:01:43 -0500 Received: by mail-wr1-f68.google.com with SMTP id u9-v6so2450764wrr.0; Tue, 20 Nov 2018 07:32:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8fmPV76fUFYlvWzkSd9ouZCSa7SztME68FYrhU194LE=; b=IXJzw3xLLWyVnUtDavYmq4ueWIIDNwpQVqDVQRHWJDX8krueN5967CsQNU6wwhl1Gf REr57XEQft75kULzObQaIe/IP0n8FG8Yrx5STN8PaEEf4JslVOv3horc74oGBMnjQoVO oXU9sk+4XbOWmymGojymE2Fykw/DWUfR0x4XxXSAH90/wpnTgn5lqn7hJ9XryhIQvvyo p1zFTq4fgqHneQE8beZsHu84JNI7ZvrYkDDXpJnjWwPM1jFtXmTxnsOGFbaUoMDfdg/2 arP5ksDOHh5/QfmV0TMeX3/sRxW1YvdlDLTRjfvIUnjHGtKnXRPwCAkB+FWSQAEHPM4u AZ6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8fmPV76fUFYlvWzkSd9ouZCSa7SztME68FYrhU194LE=; b=ueBK8tyqhwyefj1JjhF2WBz7S01IadXbWFFp6YKem9WxpkSPs5g4do0v7jqbN+Zu7x O7eBB8ZH+/7+Rx6WLBfC+VMN4L9zPrA8LqdeqofhnUoO5iDWxC5jqw81ez7Pojy3uaBj Jd5pemrwzxg0zcmZh33syZfjFGaZP2ph525bw/bKefWXlvKAeNU4JBkWeW/lNwlxz+0j LtoAes5nKcqYkWssE6jdizgAQxRUYaoOTGUxyCwwsOig6t1ywTZI838bBBfDlXxPZ8fM UHJ4+4Hd1Kl+sgN/z+N2ctYGvhPQPzzXCkPEx7GG/3+Kmhrac9WkzWU6Yqarfzq5Ty8S BBww== X-Gm-Message-State: AA+aEWYv9wKS3H46yIUMIGHFxWdR0/MTWnHSCq+l6HeLVjlBndU1wJh5 ZnjChmx2QtNUdww0xnOJoHE= X-Received: by 2002:adf:c5c2:: with SMTP id v2-v6mr2381171wrg.30.1542727920127; Tue, 20 Nov 2018 07:32:00 -0800 (PST) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.gmail.com with ESMTPSA id k73sm14677464wmd.36.2018.11.20.07.31.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 07:31:59 -0800 (PST) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v6 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors Date: Tue, 20 Nov 2018 16:31:46 +0100 Message-Id: <20181120153151.18024-2-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181120153151.18024-1-andrea.merello@gmail.com> References: <20181120153151.18024-1-andrea.merello@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Whenever a single or cyclic transaction is prepared, the driver could eventually split it over several SG descriptors in order to deal with the HW maximum transfer length. This could end up in DMA operations starting from a misaligned address. This seems fatal for the HW if DRE (Data Realignment Engine) is not enabled. This patch eventually adjusts the transfer size in order to make sure all operations start from an aligned address. Cc: Radhey Shyam Pandey Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey --- Changes in v2: - don't introduce copy_mask field, rather rely on already-esistent copy_align field. Suggested by Radhey Shyam Pandey - reword title Changes in v3: - fix bug introduced in v2: wrong copy size when DRE is enabled - use implementation suggested by Radhey Shyam Pandey Changes in v4: - rework on the top of 1/6 Changes in v5: - fix typo in commit title - add hint about "DRE" meaning in commit message Changes in v6: None --- drivers/dma/xilinx/xilinx_dma.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 2c1db500284f..cbf34dd5e966 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -975,6 +975,15 @@ static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, copy = min_t(size_t, size - done, chan->xdev->max_buffer_len); + if ((copy + done < size) && + chan->xdev->common.copy_align) { + /* + * If this is not the last descriptor, make sure + * the next one will be properly aligned + */ + copy = rounddown(copy, + (1 << chan->xdev->common.copy_align)); + } return copy; } -- 2.17.1