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[209.132.180.67]) by mx.google.com with ESMTP id j14si4225522pgi.354.2018.11.20.12.30.10; Tue, 20 Nov 2018 12:30:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kylehuey.com header.s=google header.b=H1N3wco9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727511AbeKUG0R (ORCPT + 99 others); Wed, 21 Nov 2018 01:26:17 -0500 Received: from mail-vs1-f65.google.com ([209.85.217.65]:44845 "EHLO mail-vs1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727384AbeKUG0R (ORCPT ); Wed, 21 Nov 2018 01:26:17 -0500 Received: by mail-vs1-f65.google.com with SMTP id g68so1824977vsd.11 for ; Tue, 20 Nov 2018 11:55:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kylehuey.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=kYVR6WxMSD2Ly1obkFCk4J7fsBZbqRtYof4ux6e/Pcw=; b=H1N3wco95Fro27YYiZCg8/b9YZ70PIHWolfSQjrLdwl25EAkUP7hZPLYS86ZhuiBqW stfef/y79JA+4ZIi4f8N+F2tMoPsvlM1mYehkiee45Uh6bvVV+TWmqJkB7GiBR2dxzKa WwpoG04rp3OHzNVOYTtsXBbPEv2v6p8QQa2wZHLUwD+SjM7JRxFbdHeiej28N3pgDzJZ Pq2DNqbzNhIkJfTb+f/70gxmpdqh6CU8XVLs2M3yGGhfQaDdius/jQFxXJQlgHUEo6w3 lWn231VaeK/jsqWxK6zfMuGtgD+qSmsCFdpDjtya7vdX79aciC9ItxVHenlVfxxMBzi2 TUSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=kYVR6WxMSD2Ly1obkFCk4J7fsBZbqRtYof4ux6e/Pcw=; b=Rg5G/iLat/PWCn12AwDebEHLByzlO+XABpePkEXIeKsDiCnq0wLWMx5U8Iv0qX8YAo SFUqeHhkufdizlP2m1ZsY056pvIMEmPLjEchObvAFW2Z1yBmI321ARiI1cFTV7bFr+dQ o4s7YSvWJLbppyq5ARTEkDL+WkGRPcuRgIVHXbABz7fG/MZX8PIS+kk3reWmpvH+n9k3 S7KSbOTMfiQJI/+MypZALFltGOyDqIVuQF7CKBJR1Cqk+IYvk9TvRCq4j5G/4MiKGv6+ Q0bR0Qq+yfEuYmD/MPSszR6819ryjfcxWrm05ntRQmCbME5Rxi8NPMVYb80lotvvDV6L joEA== X-Gm-Message-State: AGRZ1gJaCaCZJoE3CMBI28P58ehRHZZx4HGxQ4TiZVuhz0IIolqdUGhX 61ePov41cCSoVDOQP5oZvkRgUT/5NrwlH+iFVETqJA== X-Received: by 2002:a67:db06:: with SMTP id z6mr1476864vsj.73.1542743725946; Tue, 20 Nov 2018 11:55:25 -0800 (PST) MIME-Version: 1.0 References: <20181120194129.GC13936@tassilo.jf.intel.com> In-Reply-To: <20181120194129.GC13936@tassilo.jf.intel.com> From: Kyle Huey Date: Tue, 20 Nov 2018 11:54:56 -0800 Message-ID: Subject: Re: [REGRESSION] x86, perf: counter freezing breaks rr To: Andi Kleen Cc: Kan Liang , "Peter Zijlstra (Intel)" , Ingo Molnar , "Robert O'Callahan" , Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , Linus Torvalds , Stephane Eranian , Thomas Gleixner , Vince Weaver , acme@kernel.org, open list Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 20, 2018 at 11:41 AM Andi Kleen wrote: > > > rr, a userspace record and replay debugger[0], uses the PMU interrupt > > (PMI) to stop a program during replay to inject asynchronous events > > such as signals. With perf counter freezing enabled we are reliably > > seeing perf event overcounts during replay. This behavior is easily > > It's hard to see how it could over count since the PMU freezes > earlier than the PMI with freezing. So it should count less. > Did you mean under count? Yes, I did mean under count, see my last email. > > Given that we're already at rc3, and that this renders rr unusable, > > we'd ask that counter freezing be disabled for the 4.20 release. > > The boot option should be good enough for the release? I'm not entirely sure what you mean here. We want you to flip the default boot option so this feature is off for this release. i.e. rr should work by default on 4.20 and people should have to opt into the inaccurate behavior if they want faster PMI servicing. > A reasonable future option would be to expose an option to disable it in > the perf_event. Then rr could set it. - Kyle