Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp1326060imu; Tue, 20 Nov 2018 15:51:26 -0800 (PST) X-Google-Smtp-Source: AJdET5cSaJWnVNed9eXlqwE2wlH7Ekv3hIie3bDPSKcgthqz0QDkxwGEAr6eWmrUNOr781mo3EJB X-Received: by 2002:a62:2bd4:: with SMTP id r203-v6mr4362299pfr.105.1542757886158; Tue, 20 Nov 2018 15:51:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542757886; cv=none; d=google.com; s=arc-20160816; b=PqOOx8bWnGVX/nchxA9xkfGqnyTrlVgnQHjvb65V8YhHiASJ5Iddn+JU02eKjPC+Cm aTr3agsCaxBsmnvYvl4Mde8o0M5wRNjZjVlEb/I8hcyugjn5pwQD4C/Z9r1HgPN6XNxJ IY/f51SJjq7uZVGgeF2fOlGxnwBM9ZSoUgJahr8yXcX1Hq6j7hgX6mpJvlmVFfr4suvf W/I001916lQCjQxwB/ghjVHigcyZEjwBEq5Pj3oa82om7ZnHk/GfjN0VwJqbe35TybIc AIsm33g7G1tYgi7F2TMQNlVhHeJqdOwbn2BVZOtrIdxx4LdRQNeGC/oZpLdz6HdcVN16 7zaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject; bh=JgtfNA9tOwVDXMOFUzOwRsBNGYMiYHJJQcNvh32SpDg=; b=Vq+Fqjfk1MOwqiKfgLz3Kmka6yS3L7O1FCE+2CraoqCAz+ruDtFNuakZSWdWCvO1YE YuzDy/a2KAGburtV2XNZiOuph8PDaOZHPzSzCTOWja0ItIwz2UZUVRSDO1xh0oqjUSI9 O9I0Psc4b6A9God/rCgnc3DA5f3tkJU50toopLIuMPpGr6X6lcZ37YHPyKChTWWZmKYv l+Z0kKuvYMgwoy1IlYG2k7nOM8ie7bmFKffejSegwOSqDG6Vdyzq0EoV6CLa7po22sAA 8SiqvpRyNOWbZ+s5pqAU5w1T2n5/GOErzEkQe8DRD9379MAAM/D8VSNvbNbzu+/MhgQW a2Hw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u4si26938312pls.200.2018.11.20.15.51.10; Tue, 20 Nov 2018 15:51:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726620AbeKUKPo (ORCPT + 99 others); Wed, 21 Nov 2018 05:15:44 -0500 Received: from mga12.intel.com ([192.55.52.136]:12404 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725913AbeKUKPo (ORCPT ); Wed, 21 Nov 2018 05:15:44 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Nov 2018 15:43:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,258,1539673200"; d="scan'208";a="97837766" Received: from avandeve-mobl.amr.corp.intel.com (HELO [10.249.65.218]) ([10.249.65.218]) by FMSMGA003.fm.intel.com with ESMTP; 20 Nov 2018 15:43:54 -0800 Subject: Re: STIBP by default.. Revert? To: Jiri Kosina Cc: Linus Torvalds , Thomas Gleixner , Peter Zijlstra , Josh Poimboeuf , Andrea Arcangeli , David Woodhouse , Andi Kleen , Tim Chen , "Schaufler, Casey" , Linux List Kernel Mailing , the arch/x86 maintainers , "stable@vger.kernel.org" References: <51127fd4-5dcc-b2b9-4873-72098d2a77d9@linux.intel.com> From: Arjan van de Ven Message-ID: <6624874d-3e5b-1d41-7962-9291dd2eaa1a@linux.intel.com> Date: Wed, 21 Nov 2018 07:43:50 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/20/2018 11:27 PM, Jiri Kosina wrote: > On Mon, 19 Nov 2018, Arjan van de Ven wrote: > >> In the documentation, AMD officially recommends against this by default, >> and I can speak for Intel that our position is that as well: this really >> must not be on by default. > > Thanks for pointing to the AMD doc, it's indeed clearly stated there. > > Is there any chance this could perhaps be added to Intel documentation as > well, so that we avoid cases like this in the future? absolutely that's now already in progress; the doc publishing process is a bit on the long side unfortunately so it won't be today ;)