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From:   Dave Rodgman <dave.rodgman@arm.com>
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Subject: [PATCH 2/6] lib/lzo: enable 64-bit CTZ on Arm
Thread-Topic: [PATCH 2/6] lib/lzo: enable 64-bit CTZ on Arm
Thread-Index: AQHUgZGqN6pzoQP0L0WMU+nhfE9TCQ==
Date:   Wed, 21 Nov 2018 11:59:32 +0000
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From: Matt Sealey <matt.sealey@arm.com>

ARMv6 Thumb state introduced an RBIT instruction which, combined with CLZ
as present in ARMv5, introduces an extremely fast path for counting
trailing zeroes.

Enable the use of the GCC builtin for this on ARMv6+ with
CONFIG_THUMB2_KERNEL to ensure we get the 'new' instruction usage.

We do not bother enabling LZO_USE_CTZ64 support for ARMv5 as the builtin
code path does the same thing as the LZO_USE_CTZ32 code, only with more
register pressure.

Signed-off-by: Matt Sealey <matt.sealey@arm.com>
---
 lib/lzo/lzodefs.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/lib/lzo/lzodefs.h b/lib/lzo/lzodefs.h
index 9f167eaabb28..a9927bbce21f 100644
--- a/lib/lzo/lzodefs.h
+++ b/lib/lzo/lzodefs.h
@@ -33,9 +33,14 @@
 #define LZO_USE_CTZ32	1
 #elif defined(__i386__) || defined(__powerpc__)
 #define LZO_USE_CTZ32	1
-#elif defined(__arm__) && (__LINUX_ARM_ARCH__ >=3D 5)
+#elif defined(__arm__)
+#if (__LINUX_ARM_ARCH__ >=3D 5)
 #define LZO_USE_CTZ32	1
 #endif
+#if (__LINUX_ARM_ARCH__ >=3D 6) && (CONFIG_THUMB2_KERNEL)
+#define LZO_USE_CTZ64	1
+#endif
+#endif
=20
 #define M1_MAX_OFFSET	0x0400
 #define M2_MAX_OFFSET	0x0800
--=20
2.16.4