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[209.132.180.67]) by mx.google.com with ESMTP id w6si8335754pfb.191.2018.11.21.10.38.19; Wed, 21 Nov 2018 10:38:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732108AbeKVDpM (ORCPT + 99 others); Wed, 21 Nov 2018 22:45:12 -0500 Received: from smtp.nue.novell.com ([195.135.221.5]:38876 "EHLO smtp.nue.novell.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725995AbeKVDpM (ORCPT ); Wed, 21 Nov 2018 22:45:12 -0500 Received: from ziggy.stardust ([37.223.147.230]) by smtp.nue.novell.com with ESMTP (TLS encrypted); Wed, 21 Nov 2018 18:09:53 +0100 Subject: Re: [PATCH v5 08/12] dt-bindings: mediatek: Change the binding for mmsys clocks To: Stephen Boyd , Matthias Brugger , Rob Herring Cc: matthias.bgg@kernel.org, Mark Rutland , CK Hu , Philipp Zabel , David Airlie , Michael Turquette , Stephen Boyd , Ulrich Hecht , Laurent Pinchart , Sean Wang , Sean Wang , Randy Dunlap , Chen-Yu Tsai , dri-devel , "linux-kernel@vger.kernel.org" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , linux-mediatek@lists.infradead.org, linux-clk , devicetree@vger.kernel.org References: <20181116125449.23581-1-matthias.bgg@kernel.org> <20181116125449.23581-9-matthias.bgg@kernel.org> <20181116231522.GA18006@bogus> <2a23e407-4cd4-2e2b-97a5-4e2bb96846e0@gmail.com> <154281878765.88331.10581984256202566195@swboyd.mtv.corp.google.com> From: Matthias Brugger Openpgp: preference=signencrypt Autocrypt: addr=mbrugger@suse.com; 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Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.3.0 MIME-Version: 1.0 In-Reply-To: <154281878765.88331.10581984256202566195@swboyd.mtv.corp.google.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21/11/2018 17:46, Stephen Boyd wrote: > Quoting Rob Herring (2018-11-19 11:15:16) >> On Sun, Nov 18, 2018 at 11:12 AM Matthias Brugger >> wrote: >>> On 11/17/18 12:15 AM, Rob Herring wrote: >>>> On Fri, Nov 16, 2018 at 01:54:45PM +0100, matthias.bgg@kernel.org wrote: >>>>> - #clock-cells = <1>; >>>>> + >>>>> + mmsys_clk: clock-controller@14000000 { >>>>> + compatible = "mediatek,mt2712-mmsys-clk"; >>>>> + #clock-cells = <1>; >>>> >>>> This goes against the general direction of not defining separate nodes >>>> for providers with no resources. >>>> >>>> Why do you need this and what does it buy if you have to continue to >>>> support the existing chips? >>>> >>> >>> It would show explicitly that the mmsys block is used to probe two >>> drivers, one for the gpu and one for the clocks. Otherwise that is >>> hidden in the drm driver code. I think it is cleaner to describe that in >>> the device tree. >> >> No, that's maybe cleaner for the driver implementation in the Linux >> kernel. What about other OS's or when Linux drivers and subsystems >> needs change? Cleaner for DT is design bindings that reflect the h/w. >> Hardware is sometimes just messy. >> > > I agree. I fail to see what this patch series is doing besides changing > driver probe and device creation methods and making a backwards > incompatible change to DT. Is there any other benefit here? > You are referring whole series? Citing the cover letter: "MMSYS in Mediatek SoCs has some registers to control clock gates (which is used in the clk driver) and some registers to set the routing and enable the differnet (sic!) blocks of the display subsystem. Up to now both drivers, clock and drm are probed with the same device tree compatible. But only the first driver get probed, which in effect breaks graphics on mt8173 and mt2701. This patch uses a platform device registration in the DRM driver, which will trigger the probe of the corresponding clock driver. It was tested on the bananapi-r2 and the Acer R13 Chromebook." DT is broken right now, because two drivers rely on the same node, which gets consumed just once. The new DT introduced does not break anything because it is only used for boards that: "[..] are not available to the general public (mt2712e) or only have the mmsys clock driver part implemented (mt6797)." Anyway, I'll send a new version which uses the platform device in the DRM driver for all SoCs. Regards, Matthias