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Subject: [PATCH v9 04/13] x86/resctrl: Bring all the macros to
 resctrl/internal.h
Thread-Topic: [PATCH v9 04/13] x86/resctrl: Bring all the macros to
 resctrl/internal.h
Thread-Index: AQHUgdjElIXMJYGTbUalTNfAFHBakA==
Date:   Wed, 21 Nov 2018 20:28:31 +0000
Message-ID: <20181121202811.4492-5-babu.moger@amd.com>
References: <20181121202811.4492-1-babu.moger@amd.com>
In-Reply-To: <20181121202811.4492-1-babu.moger@amd.com>
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Bring all the macros to resctrl/internal.h and rename the
registers with MSR_ prefix for consistency.

Signed-off-by: Babu Moger <babu.moger@amd.com>
---
 arch/x86/kernel/cpu/resctrl/core.c     | 22 ++++++++++------------
 arch/x86/kernel/cpu/resctrl/internal.h | 15 ++++++++++-----
 arch/x86/kernel/cpu/resctrl/monitor.c  |  3 ---
 arch/x86/kernel/cpu/resctrl/rdtgroup.c |  4 ++--
 4 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct=
rl/core.c
index 40380731c588..cf6491eeadc6 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -33,9 +33,6 @@
 #include <asm/resctrl_sched.h>
 #include "internal.h"
=20
-#define MBA_IS_LINEAR	0x4
-#define MBA_MAX_MBPS	U32_MAX
-
 /* Mutex to protect rdtgroup access. */
 DEFINE_MUTEX(rdtgroup_mutex);
=20
@@ -72,7 +69,7 @@ struct rdt_resource rdt_resources_all[] =3D {
 		.rid			=3D RDT_RESOURCE_L3,
 		.name			=3D "L3",
 		.domains		=3D domain_init(RDT_RESOURCE_L3),
-		.msr_base		=3D IA32_L3_CBM_BASE,
+		.msr_base		=3D MSR_IA32_L3_CBM_BASE,
 		.msr_update		=3D cat_wrmsr,
 		.cache_level		=3D 3,
 		.cache =3D {
@@ -89,7 +86,7 @@ struct rdt_resource rdt_resources_all[] =3D {
 		.rid			=3D RDT_RESOURCE_L3DATA,
 		.name			=3D "L3DATA",
 		.domains		=3D domain_init(RDT_RESOURCE_L3DATA),
-		.msr_base		=3D IA32_L3_CBM_BASE,
+		.msr_base		=3D MSR_IA32_L3_CBM_BASE,
 		.msr_update		=3D cat_wrmsr,
 		.cache_level		=3D 3,
 		.cache =3D {
@@ -106,7 +103,7 @@ struct rdt_resource rdt_resources_all[] =3D {
 		.rid			=3D RDT_RESOURCE_L3CODE,
 		.name			=3D "L3CODE",
 		.domains		=3D domain_init(RDT_RESOURCE_L3CODE),
-		.msr_base		=3D IA32_L3_CBM_BASE,
+		.msr_base		=3D MSR_IA32_L3_CBM_BASE,
 		.msr_update		=3D cat_wrmsr,
 		.cache_level		=3D 3,
 		.cache =3D {
@@ -123,7 +120,7 @@ struct rdt_resource rdt_resources_all[] =3D {
 		.rid			=3D RDT_RESOURCE_L2,
 		.name			=3D "L2",
 		.domains		=3D domain_init(RDT_RESOURCE_L2),
-		.msr_base		=3D IA32_L2_CBM_BASE,
+		.msr_base		=3D MSR_IA32_L2_CBM_BASE,
 		.msr_update		=3D cat_wrmsr,
 		.cache_level		=3D 2,
 		.cache =3D {
@@ -140,7 +137,7 @@ struct rdt_resource rdt_resources_all[] =3D {
 		.rid			=3D RDT_RESOURCE_L2DATA,
 		.name			=3D "L2DATA",
 		.domains		=3D domain_init(RDT_RESOURCE_L2DATA),
-		.msr_base		=3D IA32_L2_CBM_BASE,
+		.msr_base		=3D MSR_IA32_L2_CBM_BASE,
 		.msr_update		=3D cat_wrmsr,
 		.cache_level		=3D 2,
 		.cache =3D {
@@ -157,7 +154,7 @@ struct rdt_resource rdt_resources_all[] =3D {
 		.rid			=3D RDT_RESOURCE_L2CODE,
 		.name			=3D "L2CODE",
 		.domains		=3D domain_init(RDT_RESOURCE_L2CODE),
-		.msr_base		=3D IA32_L2_CBM_BASE,
+		.msr_base		=3D MSR_IA32_L2_CBM_BASE,
 		.msr_update		=3D cat_wrmsr,
 		.cache_level		=3D 2,
 		.cache =3D {
@@ -174,7 +171,7 @@ struct rdt_resource rdt_resources_all[] =3D {
 		.rid			=3D RDT_RESOURCE_MBA,
 		.name			=3D "MB",
 		.domains		=3D domain_init(RDT_RESOURCE_MBA),
-		.msr_base		=3D IA32_MBA_THRTL_BASE,
+		.msr_base		=3D MSR_IA32_MBA_THRTL_BASE,
 		.msr_update		=3D mba_wrmsr,
 		.cache_level		=3D 3,
 		.parse_ctrlval		=3D parse_bw,
@@ -211,9 +208,10 @@ static inline void cache_alloc_hsw_probe(void)
 	struct rdt_resource *r  =3D &rdt_resources_all[RDT_RESOURCE_L3];
 	u32 l, h, max_cbm =3D BIT_MASK(20) - 1;
=20
-	if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
+	if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0))
 		return;
-	rdmsr(IA32_L3_CBM_BASE, l, h);
+
+	rdmsr(MSR_IA32_L3_CBM_BASE, l, h);
=20
 	/* If all the bits were set in MSR, return success */
 	if (l !=3D max_cbm)
diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r=
esctrl/internal.h
index eeaee05522b5..cac360169205 100644
--- a/arch/x86/kernel/cpu/resctrl/internal.h
+++ b/arch/x86/kernel/cpu/resctrl/internal.h
@@ -6,11 +6,14 @@
 #include <linux/kernfs.h>
 #include <linux/jump_label.h>
=20
-#define IA32_L3_QOS_CFG		0xc81
-#define IA32_L2_QOS_CFG		0xc82
-#define IA32_L3_CBM_BASE	0xc90
-#define IA32_L2_CBM_BASE	0xd10
-#define IA32_MBA_THRTL_BASE	0xd50
+#define MSR_IA32_L3_QOS_CFG	0xc81
+#define MSR_IA32_L2_QOS_CFG	0xc82
+#define MSR_IA32_L3_CBM_BASE	0xc90
+#define MSR_IA32_L2_CBM_BASE	0xd10
+#define MSR_IA32_MBA_THRTL_BASE 0xd50
+
+#define MSR_IA32_QM_CTR		0x0c8e
+#define MSR_IA32_QM_EVTSEL	0x0c8d
=20
 #define L3_QOS_CDP_ENABLE	0x01ULL
=20
@@ -29,6 +32,8 @@
 #define MBM_CNTR_WIDTH			24
 #define MBM_OVERFLOW_INTERVAL		1000
 #define MAX_MBA_BW			100u
+#define MBA_IS_LINEAR			0x4
+#define MBA_MAX_MBPS			U32_MAX
=20
 #define RMID_VAL_ERROR			BIT_ULL(63)
 #define RMID_VAL_UNAVAIL		BIT_ULL(62)
diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re=
sctrl/monitor.c
index ebf408db8191..f33f11f69078 100644
--- a/arch/x86/kernel/cpu/resctrl/monitor.c
+++ b/arch/x86/kernel/cpu/resctrl/monitor.c
@@ -28,9 +28,6 @@
 #include <asm/cpu_device_id.h>
 #include "internal.h"
=20
-#define MSR_IA32_QM_CTR		0x0c8e
-#define MSR_IA32_QM_EVTSEL		0x0c8d
-
 struct rmid_entry {
 	u32				rmid;
 	int				busy;
diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r=
esctrl/rdtgroup.c
index 2bf1f3227afa..cf159095b612 100644
--- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
+++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
@@ -1722,14 +1722,14 @@ static void l3_qos_cfg_update(void *arg)
 {
 	bool *enable =3D arg;
=20
-	wrmsrl(IA32_L3_QOS_CFG, *enable ? L3_QOS_CDP_ENABLE : 0ULL);
+	wrmsrl(MSR_IA32_L3_QOS_CFG, *enable ? L3_QOS_CDP_ENABLE : 0ULL);
 }
=20
 static void l2_qos_cfg_update(void *arg)
 {
 	bool *enable =3D arg;
=20
-	wrmsrl(IA32_L2_QOS_CFG, *enable ? L2_QOS_CDP_ENABLE : 0ULL);
+	wrmsrl(MSR_IA32_L2_QOS_CFG, *enable ? L2_QOS_CDP_ENABLE : 0ULL);
 }
=20
 static inline bool is_mba_linear(void)
--=20
2.17.1