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Date:   Thu, 22 Nov 2018 09:43:48 +0100
From:   Maxime Ripard <maxime.ripard@bootlin.com>
To:     Mesih Kilinc <mesihkilinc@gmail.com>
Cc:     devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com,
        Chen-Yu Tsai <wens@csie.org>,
        Russell King <linux@armlinux.org.uk>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Marc Zyngier <marc.zyngier@arm.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        Icenowy Zheng <icenowy@aosc.io>,
        Rob Herring <robh+dt@kernel.org>,
        Julian Calaby <julian.calaby@gmail.com>,
        Mesih Kilinc <mesihkilnc@gmail.com>
Subject: Re: [RFC PATCH v3 16/17] ARM: dts: suniv: add initial DTSI file for
 F1C100s
Message-ID: <20181122084348.fls7th5psdqulncl@flea>
References: <cover.1542824904.git.mesihkilinc@gmail.com>
 <05dab577154c72117678c2f49ae85a9663a630e2.1542824904.git.mesihkilinc@gmail.com>
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On Wed, Nov 21, 2018 at 09:30:49PM +0300, Mesih Kilinc wrote:
> F1C100s is one product with the suniv die, which has a 32MiB co-packaged
> DDR1 DRAM chip. As we have the support for suniv pin controller and CCU n=
ow, add a
> initial DTSI for it.
>=20
> Signed-off-by: Mesih Kilinc <mesihkilnc@gmail.com>
> ---
>  arch/arm/boot/dts/suniv-f1c100s.dtsi | 151 +++++++++++++++++++++++++++++=
++++++
>  1 file changed, 151 insertions(+)
>  create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi
>=20
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/sun=
iv-f1c100s.dtsi
> new file mode 100644
> index 0000000..3ad64ee
> --- /dev/null
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -0,0 +1,151 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
> +/*
> + * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
> + * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
> + */
> +
> +#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
> +#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
> +
> +/ {
> +	#address-cells =3D <1>;
> +	#size-cells =3D <1>;
> +	interrupt-parent =3D <&intc>;
> +
> +	clocks {
> +		#address-cells =3D <1>;
> +		#size-cells =3D <1>;
> +		ranges;
> +
> +		osc24M: clk-24M {
> +			#clock-cells =3D <0>;
> +			compatible =3D "fixed-clock";
> +			clock-frequency =3D <24000000>;
> +			clock-output-names =3D "osc24M";
> +		};
> +
> +		osc32k: clk-32k {
> +			#clock-cells =3D <0>;
> +			compatible =3D "fixed-clock";
> +			clock-frequency =3D <32768>;
> +			clock-output-names =3D "osc32k";
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells =3D <0>;
> +		#size-cells =3D <0>;

I don't think you need those two properties (and the for the clocks as
well). Ideally, if you could compile the dtbs with W=3D1, and fix any
warning, that would be awesome. We're trying to get rid of them, so
let's not add some new ones.

> +		cpu {
> +			compatible =3D "arm,arm926ej-s";
> +			device_type =3D "cpu";
> +		};
> +	};
> +
> +	soc {
> +		compatible =3D "simple-bus";
> +		#address-cells =3D <1>;
> +		#size-cells =3D <1>;
> +		ranges;
> +
> +		sram-controller@1c00000 {
> +			compatible =3D "allwinner,suniv-f1c100s-system-control";
> +			reg =3D <0x01c00000 0x30>;
> +			#address-cells =3D <1>;
> +			#size-cells =3D <1>;
> +			ranges;
> +
> +			sram_d: sram@10000 {
> +				compatible =3D "mmio-sram";
> +				reg =3D <0x00010000 0x1000>;
> +				#address-cells =3D <1>;
> +				#size-cells =3D <1>;
> +				ranges =3D <0 0x00010000 0x1000>;
> +
> +				otg_sram: sram-section@0 {
> +					compatible =3D "allwinner,suniv-f1c100s-sram-d";
> +					reg =3D <0x0000 0x1000>;
> +					status =3D "disabled";
> +				};
> +			};
> +		};
> +
> +		ccu: clock@1c20000 {
> +			compatible =3D "allwinner,suniv-f1c100s-ccu";
> +			reg =3D <0x01c20000 0x400>;
> +			clocks =3D <&osc24M>, <&osc32k>;
> +			clock-names =3D "hosc", "losc";
> +			#clock-cells =3D <1>;
> +			#reset-cells =3D <1>;
> +		};
> +
> +		intc: interrupt-controller@1c20400 {
> +			compatible =3D "allwinner,suniv-f1c100s-ic";
> +			reg =3D <0x01c20400 0x400>;
> +			interrupt-controller;
> +			#interrupt-cells =3D <1>;
> +		};
> +
> +		pio: pinctrl@1c20800 {
> +			compatible =3D "allwinner,suniv-f1c100s-pinctrl";
> +			reg =3D <0x01c20800 0x400>;
> +			interrupts =3D <38>, <39>, <40>;
> +			clocks =3D <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
> +			clock-names =3D "apb", "hosc", "losc";
> +			gpio-controller;
> +			interrupt-controller;
> +			#interrupt-cells =3D <3>;
> +			#gpio-cells =3D <3>;
> +
> +			uart0_pins_a: uart-pins-pe {
> +				pins =3D "PE0", "PE1";
> +				function =3D "uart0";
> +			};
> +		};
> +
> +		timer@1c20c00 {
> +			compatible =3D "allwinner,suniv-f1c100s-timer";
> +			reg =3D <0x01c20c00 0x90>;
> +			interrupts =3D <13>;
> +			clocks =3D <&osc24M>;
> +		};
> +
> +		wdt: watchdog@1c20ca0 {
> +			compatible =3D "allwinner,suniv-f1c100s-wdt";

If you don't have any difference with the A31 watchdog (and this is
the same case for the A10 system controller and SRAM's), you can just have

compatible =3D "allwinner,suniv-f1c100s-wdt", "allwinner,sun6i-a31-wdt";

This way, you don't have to patch the driver to add the compatible, it
will fall back to the A31 one (just make sure to document this
properly in the binding doc, you can follow the A64 example).

Thanks!
Maxime

--=20
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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