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[209.132.180.67]) by mx.google.com with ESMTP id k5si18790491pfi.176.2018.11.23.15.03.19; Fri, 23 Nov 2018 15:04:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b=tZOFAEH7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2437600AbeKWB7e (ORCPT + 99 others); Thu, 22 Nov 2018 20:59:34 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:45713 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731279AbeKWB7e (ORCPT ); Thu, 22 Nov 2018 20:59:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date; bh=t4lJXZS95oUH104pGtmd//yuZEh99+M7Tq15NPLR90c=; b=tZOFAEH7vac0PvgCod69bwYwvyIZo6yWcL3ndZpPjkSdVXP94gAlPsEtQJxgeqE60PBMpir6lXB2Roe0CA/qmni4UCys+NT4+B5IyfHAAlpRJlBqhLXoGRgLKwnx/FD7U74cjybm8cSgMIwJ6PNgOVv43EmXqTWaRKFspnpqJUA=; Received: from andrew by vps0.lunn.ch with local (Exim 4.84_2) (envelope-from ) id 1gPqlQ-0000Xp-Vp; Thu, 22 Nov 2018 16:19:33 +0100 Date: Thu, 22 Nov 2018 16:19:32 +0100 From: Andrew Lunn To: Biao Huang Cc: davem@davemloft.net, robh+dt@kernel.org, honghui.zhang@mediatek.com, yt.shen@mediatek.com, liguo.zhang@mediatek.com, mark.rutland@arm.com, nelson.chang@mediatek.com, matthias.bgg@gmail.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, joabreu@synopsys.com Subject: Re: [v5, PATCH 2/2] dt-binding: mediatek-dwmac: add binding document for MediaTek MT2712 DWMAC Message-ID: <20181122151932.GD15403@lunn.ch> References: <1542882521-18874-1-git-send-email-biao.huang@mediatek.com> <1542882521-18874-3-git-send-email-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1542882521-18874-3-git-send-email-biao.huang@mediatek.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 22, 2018 at 06:28:41PM +0800, Biao Huang wrote: > The commit adds the device tree binding documentation for the MediaTek DWMAC > found on MediaTek MT2712. > > Signed-off-by: Biao Huang > +Optional properties: > +- mediatek,tx-delay: TX clock delay macro value. Range is 0~31. Default is 0. > + It should be defined for rgmii/rgmii-rxid/mii interface. > +- mediatek,rx-delay: RX clock delay macro value. Range is 0~31. Default is 0. > + It should be defined for rgmii/rgmii-txid/mii/rmii interface. You have received the same feedback at least twice now, from two different maintainers, that the delay should be specified in pS, and the driver should figure out what values to place into registers. You should not ignore feedback like that. If you don't understand the feedback, please ask us to explain it. If you don't agree with the feedback, you need to argue why you think it is wrong, or why what you are doing is better, etc. We are here to help, but just ignoring us won't get you anywhere. For the moment: NACK Andrew