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[209.132.180.67]) by mx.google.com with ESMTP id s59si16339614plb.237.2018.11.23.23.43.42; Fri, 23 Nov 2018 23:43:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2407635AbeKWI37 (ORCPT + 99 others); Fri, 23 Nov 2018 03:29:59 -0500 Received: from terminus.zytor.com ([198.137.202.136]:48687 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2392384AbeKWI37 (ORCPT ); Fri, 23 Nov 2018 03:29:59 -0500 Received: from terminus.zytor.com (localhost [127.0.0.1]) by terminus.zytor.com (8.15.2/8.15.2) with ESMTPS id wAMLlfBX3947149 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 22 Nov 2018 13:47:41 -0800 Received: (from tipbot@localhost) by terminus.zytor.com (8.15.2/8.15.2/Submit) id wAMLlfho3947145; Thu, 22 Nov 2018 13:47:41 -0800 Date: Thu, 22 Nov 2018 13:47:41 -0800 X-Authentication-Warning: terminus.zytor.com: tipbot set sender to tipbot@zytor.com using -f From: tip-bot for Babu Moger Message-ID: Cc: pbonzini@redhat.com, chang.seok.bae@intel.com, hpa@zytor.com, jpoimboe@redhat.com, jannh@google.com, tony.luck@intel.com, babu.moger@amd.com, linux-kernel@vger.kernel.org, arnd@arndb.de, tglx@linutronix.de, reinette.chatre@intel.com, xiaochen.shen@intel.com, davem@davemloft.net, peterz@infradead.org, bp@suse.de, kstewart@linuxfoundation.org, sherry.hurwitz@amd.com, akpm@linux-foundation.org, linux-doc@vger.kernel.org, mingo@redhat.com, mchehab+samsung@kernel.org, corbet@lwn.net, dima@arista.com, pombredanne@nexb.com, Babu.Moger@amd.com, mingo@kernel.org, brijesh.singh@amd.com, fenghua.yu@intel.com, dwmw2@infradead.org, suravee.suthikulpanit@amd.com, luto@kernel.org, jroedel@suse.de, Thomas.Lendacky@amd.com, vkuznets@redhat.com, puwen@hygon.cn, gregkh@linuxfoundation.org, kirill.shutemov@linux.intel.com, qianyue.zj@alibaba-inc.com, rian@alum.mit.edu, rafael@kernel.org Reply-To: pbonzini@redhat.com, jannh@google.com, jpoimboe@redhat.com, hpa@zytor.com, chang.seok.bae@intel.com, linux-kernel@vger.kernel.org, babu.moger@amd.com, tony.luck@intel.com, xiaochen.shen@intel.com, reinette.chatre@intel.com, arnd@arndb.de, tglx@linutronix.de, bp@suse.de, peterz@infradead.org, davem@davemloft.net, kstewart@linuxfoundation.org, corbet@lwn.net, mchehab+samsung@kernel.org, akpm@linux-foundation.org, mingo@redhat.com, linux-doc@vger.kernel.org, sherry.hurwitz@amd.com, pombredanne@nexb.com, dima@arista.com, Babu.Moger@amd.com, dwmw2@infradead.org, fenghua.yu@intel.com, mingo@kernel.org, brijesh.singh@amd.com, Thomas.Lendacky@amd.com, vkuznets@redhat.com, suravee.suthikulpanit@amd.com, jroedel@suse.de, luto@kernel.org, puwen@hygon.cn, rian@alum.mit.edu, qianyue.zj@alibaba-inc.com, gregkh@linuxfoundation.org, kirill.shutemov@linux.intel.com, rafael@kernel.org In-Reply-To: <20181121202811.4492-5-babu.moger@amd.com> References: <20181121202811.4492-5-babu.moger@amd.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/cache] x86/resctrl: Move all the macros to resctrl/internal.h Git-Commit-ID: aa50453a448ad645ea05788505680aa403934aa8 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline X-Spam-Status: No, score=-2.9 required=5.0 tests=ALL_TRUSTED,BAYES_00, T_DATE_IN_FUTURE_96_Q autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on terminus.zytor.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: aa50453a448ad645ea05788505680aa403934aa8 Gitweb: https://git.kernel.org/tip/aa50453a448ad645ea05788505680aa403934aa8 Author: Babu Moger AuthorDate: Wed, 21 Nov 2018 20:28:31 +0000 Committer: Borislav Petkov CommitDate: Thu, 22 Nov 2018 20:16:19 +0100 x86/resctrl: Move all the macros to resctrl/internal.h Move all the macros to resctrl/internal.h and rename the registers with MSR_ prefix for consistency. [bp: align MSR definitions vertically ] Signed-off-by: Babu Moger Signed-off-by: Borislav Petkov Cc: Andrew Morton Cc: Andy Lutomirski Cc: Arnd Bergmann Cc: Brijesh Singh Cc: "Chang S. Bae" Cc: David Miller Cc: David Woodhouse Cc: Dmitry Safonov Cc: Fenghua Yu Cc: Greg Kroah-Hartman Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Jann Horn Cc: Joerg Roedel Cc: Jonathan Corbet Cc: Josh Poimboeuf Cc: Kate Stewart Cc: "Kirill A. Shutemov" Cc: Cc: Mauro Carvalho Chehab Cc: Paolo Bonzini Cc: Peter Zijlstra Cc: Philippe Ombredanne Cc: Pu Wen Cc: Cc: "Rafael J. Wysocki" Cc: Reinette Chatre Cc: Rian Hunter Cc: Sherry Hurwitz Cc: Suravee Suthikulpanit Cc: Thomas Gleixner Cc: Thomas Lendacky Cc: Tony Luck Cc: Vitaly Kuznetsov Cc: Link: https://lkml.kernel.org/r/20181121202811.4492-5-babu.moger@amd.com --- arch/x86/kernel/cpu/resctrl/core.c | 22 ++++++++++------------ arch/x86/kernel/cpu/resctrl/internal.h | 19 ++++++++++++------- arch/x86/kernel/cpu/resctrl/monitor.c | 3 --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 4 ++-- 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 40380731c588..cf6491eeadc6 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -33,9 +33,6 @@ #include #include "internal.h" -#define MBA_IS_LINEAR 0x4 -#define MBA_MAX_MBPS U32_MAX - /* Mutex to protect rdtgroup access. */ DEFINE_MUTEX(rdtgroup_mutex); @@ -72,7 +69,7 @@ struct rdt_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L3, .name = "L3", .domains = domain_init(RDT_RESOURCE_L3), - .msr_base = IA32_L3_CBM_BASE, + .msr_base = MSR_IA32_L3_CBM_BASE, .msr_update = cat_wrmsr, .cache_level = 3, .cache = { @@ -89,7 +86,7 @@ struct rdt_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L3DATA, .name = "L3DATA", .domains = domain_init(RDT_RESOURCE_L3DATA), - .msr_base = IA32_L3_CBM_BASE, + .msr_base = MSR_IA32_L3_CBM_BASE, .msr_update = cat_wrmsr, .cache_level = 3, .cache = { @@ -106,7 +103,7 @@ struct rdt_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L3CODE, .name = "L3CODE", .domains = domain_init(RDT_RESOURCE_L3CODE), - .msr_base = IA32_L3_CBM_BASE, + .msr_base = MSR_IA32_L3_CBM_BASE, .msr_update = cat_wrmsr, .cache_level = 3, .cache = { @@ -123,7 +120,7 @@ struct rdt_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L2, .name = "L2", .domains = domain_init(RDT_RESOURCE_L2), - .msr_base = IA32_L2_CBM_BASE, + .msr_base = MSR_IA32_L2_CBM_BASE, .msr_update = cat_wrmsr, .cache_level = 2, .cache = { @@ -140,7 +137,7 @@ struct rdt_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L2DATA, .name = "L2DATA", .domains = domain_init(RDT_RESOURCE_L2DATA), - .msr_base = IA32_L2_CBM_BASE, + .msr_base = MSR_IA32_L2_CBM_BASE, .msr_update = cat_wrmsr, .cache_level = 2, .cache = { @@ -157,7 +154,7 @@ struct rdt_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L2CODE, .name = "L2CODE", .domains = domain_init(RDT_RESOURCE_L2CODE), - .msr_base = IA32_L2_CBM_BASE, + .msr_base = MSR_IA32_L2_CBM_BASE, .msr_update = cat_wrmsr, .cache_level = 2, .cache = { @@ -174,7 +171,7 @@ struct rdt_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_MBA, .name = "MB", .domains = domain_init(RDT_RESOURCE_MBA), - .msr_base = IA32_MBA_THRTL_BASE, + .msr_base = MSR_IA32_MBA_THRTL_BASE, .msr_update = mba_wrmsr, .cache_level = 3, .parse_ctrlval = parse_bw, @@ -211,9 +208,10 @@ static inline void cache_alloc_hsw_probe(void) struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3]; u32 l, h, max_cbm = BIT_MASK(20) - 1; - if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0)) + if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0)) return; - rdmsr(IA32_L3_CBM_BASE, l, h); + + rdmsr(MSR_IA32_L3_CBM_BASE, l, h); /* If all the bits were set in MSR, return success */ if (l != max_cbm) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index eeaee05522b5..fb26d347ae6c 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -6,15 +6,18 @@ #include #include -#define IA32_L3_QOS_CFG 0xc81 -#define IA32_L2_QOS_CFG 0xc82 -#define IA32_L3_CBM_BASE 0xc90 -#define IA32_L2_CBM_BASE 0xd10 -#define IA32_MBA_THRTL_BASE 0xd50 +#define MSR_IA32_L3_QOS_CFG 0xc81 +#define MSR_IA32_L2_QOS_CFG 0xc82 +#define MSR_IA32_L3_CBM_BASE 0xc90 +#define MSR_IA32_L2_CBM_BASE 0xd10 +#define MSR_IA32_MBA_THRTL_BASE 0xd50 -#define L3_QOS_CDP_ENABLE 0x01ULL +#define MSR_IA32_QM_CTR 0x0c8e +#define MSR_IA32_QM_EVTSEL 0x0c8d -#define L2_QOS_CDP_ENABLE 0x01ULL +#define L3_QOS_CDP_ENABLE 0x01ULL + +#define L2_QOS_CDP_ENABLE 0x01ULL /* * Event IDs are used to program IA32_QM_EVTSEL before reading event @@ -29,6 +32,8 @@ #define MBM_CNTR_WIDTH 24 #define MBM_OVERFLOW_INTERVAL 1000 #define MAX_MBA_BW 100u +#define MBA_IS_LINEAR 0x4 +#define MBA_MAX_MBPS U32_MAX #define RMID_VAL_ERROR BIT_ULL(63) #define RMID_VAL_UNAVAIL BIT_ULL(62) diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index ebf408db8191..f33f11f69078 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -28,9 +28,6 @@ #include #include "internal.h" -#define MSR_IA32_QM_CTR 0x0c8e -#define MSR_IA32_QM_EVTSEL 0x0c8d - struct rmid_entry { u32 rmid; int busy; diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 2bf1f3227afa..cf159095b612 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1722,14 +1722,14 @@ static void l3_qos_cfg_update(void *arg) { bool *enable = arg; - wrmsrl(IA32_L3_QOS_CFG, *enable ? L3_QOS_CDP_ENABLE : 0ULL); + wrmsrl(MSR_IA32_L3_QOS_CFG, *enable ? L3_QOS_CDP_ENABLE : 0ULL); } static void l2_qos_cfg_update(void *arg) { bool *enable = arg; - wrmsrl(IA32_L2_QOS_CFG, *enable ? L2_QOS_CDP_ENABLE : 0ULL); + wrmsrl(MSR_IA32_L2_QOS_CFG, *enable ? L2_QOS_CDP_ENABLE : 0ULL); } static inline bool is_mba_linear(void)