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Date:   Mon, 26 Nov 2018 11:25:42 +0100
From:   Thierry Reding <treding@nvidia.com>
To:     Peter Ujfalusi <peter.ujfalusi@ti.com>
CC:     Tony Lindgren <tony@atomide.com>,
        Jon Hunter <jonathanh@nvidia.com>,
        Belisko Marek <marek.belisko@gmail.com>,
        LKML <linux-kernel@vger.kernel.org>,
        <linux-omap@vger.kernel.org>,
        "Dr. H. Nikolaus Schaller" <hns@goldelico.com>,
        Laxman Dewangan <ldewangan@nvidia.com>
Subject: Re: omap5 fixing palmas IRQ_TYPE_NONE warning leads to gpadc timeouts
Message-ID: <20181126102541.GC10878@ulmo>
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On Mon, Nov 26, 2018 at 11:49:54AM +0200, Peter Ujfalusi wrote:
> Thierry,
>=20
> On 11/26/18 11:36 AM, Thierry Reding wrote:
> > On Fri, Nov 23, 2018 at 08:48:27AM -0800, Tony Lindgren wrote:
> >> * Jon Hunter <jonathanh@nvidia.com> [181120 11:14]:
> >>> On 19/11/2018 17:14, Tony Lindgren wrote:
> >>>> Well so commit 7e9d474954f4 ("ARM: tegra: Correct polarity for
> >>>> Tegra114 PMIC interrupt") states that tegra114 inverts the
> >>>> polarity of the PMIC interrupt. So adding Jon and Thierry to Cc.
> >>>
> >>> Yes Tegra can invert the polarity of the PMIC interrupt.
> >>
> >> So is there some IP on Tegra called "Tegra PMC" that is
> >> inverting the interrupt? Or is the "Tegra PMC" that commit
> >> 7e9d474954f4 mentions just the palmas configuration for
> >> inverting the interrupt?
> >=20
> > Yes, there's indeed an IP called PMC (Power-Management Controller) on
> > Tegra. It has a special input that is usually wired up to the PMIC
> > interrupt and a bit in the control register that configures the polarity
> > of that interrupt. If the PMIC generates a low-active interrupt we
> > usually set that bit to make sure it is properly sampled by the PMC.
> >=20
> > The symptoms of this being incorrectly configured is usually an
> > interrupt storm on the PMIC interrupt, which I think typically results
> > in the system not booting at all, or taking a very long time to boot
> > because of that storm.
> >=20
> >> The problem I'm having is With omap5 where I can only get the
> >> PMIC interrupts working with IRQ_TYPE_LEVEL_HIGH if
> >> PALMAS_POLARITY_CTRL_INT_POLARITY is not set unlike for
> >> Tegra.
> >=20
> > Does somebody have access to the Palmas documentation? That should
> > pretty clearly state what the default polarity is and what it changes to
> > if you set the interrupt polarity bit.
>=20
> The register map documentation I have states the following:
> bit7 INT_POLARITY Select the polarity of the INT output line
> 0: Interrupt line (INT) is low when interrupt is pending (default) RW
> 1: Interrupt line (INT) is high when interrupt is pending
>=20
> By default the Palmas irq is active low.

That would confirm that the driver code is correct. My understanding is
that the PMC on Tegra expects a low-active IRQ from the PMIC, so we need
to invert the interrupt again in the PMC.

> > From what you're saying it sounds like either the logic is the wrong way
> > around in the Palmas MFD driver (and we correct it by switching it back
> > to the correct polarity in the PMC) or that you'd need to find some way
> > of inverting in on OMAP5.

=46rom the above it sounds like there would need to be some mechanism in
OMAP5 to invert the PMIC interrupt, similarly to how it is done in the
PMC on Tegra.

Thierry

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