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Date:   Mon, 26 Nov 2018 09:14:55 -0700
From:   Lina Iyer <ilina@codeaurora.org>
To:     Stephen Boyd <swboyd@chromium.org>
Cc:     evgreen@chromium.org, marc.zyngier@arm.com,
        linux-kernel@vger.kernel.org, rplsssn@codeaurora.org,
        linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        thierry.reding@gmail.com
Subject: Re: [RFC v3 2/3] dt-bindings: sdm845-pinctrl: add wakeup interrupt
 parent for GPIO
Message-ID: <20181126161455.GA28236@codeaurora.org>
References: <20181121000648.29262-1-ilina@codeaurora.org>
 <20181121000648.29262-3-ilina@codeaurora.org>
 <154283618199.88331.10217252750356423959@swboyd.mtv.corp.google.com>
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On Wed, Nov 21 2018 at 14:36 -0700, Stephen Boyd wrote:
>Quoting Lina Iyer (2018-11-20 16:06:47)
>> SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO
>> routed to the PDC as interrupts that can be used to wake the system up
>> from deep low power modes and suspend.
>>
>> Signed-off-by: Lina Iyer <ilina@codeaurora.org>
>> ---
>>  .../bindings/pinctrl/qcom,sdm845-pinctrl.txt  | 31 ++++++++++++++++++-
>>  1 file changed, 30 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
>> index 665aadb5ea28..bedfa0b57fa6 100644
>> --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
>> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
>> @@ -29,6 +29,17 @@ SDM845 platform.
>>         Definition: must be 2. Specifying the pin number and flags, as defined
>>                     in <dt-bindings/interrupt-controller/irq.h>
>>
>> +- wakeup-parent:
>> +       Usage: optional
>> +       Value type: <phandle>
>> +       Definition: A phandle to the wakeup interrupt controller for the SoC.
>> +
>> +- wakeup-irq:
>
>This shouldn't be needed. TLMM driver can probe for the possibility of
>wakeup capable irqs from irq allocation step. The only place we should
>need to know what TLMM pins map to what PDC lines is in the PDC driver.
>
Why? Every driver seems to translate the hardware IRQ and pass it to
it's parent. Why should this be any different ? The PDC is an interrupt
controller that just knows an interrupt port and maps it to the GIC. Not
sure, I understand the reasoning for this. It seems to add more
confusing relationship with the PDC interrupt controller, that way.

-- Lina