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To:     "Lendacky, Thomas" <Thomas.Lendacky@amd.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Andrea Arcangeli <aarcange@redhat.com>
Cc:     Linus Torvalds <torvalds@linux-foundation.org>,
        Linux List Kernel Mailing <linux-kernel@vger.kernel.org>,
        the arch/x86 maintainers <x86@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        Andrew Lutomirski <luto@kernel.org>,
        Jiri Kosina <jkosina@suse.cz>,
        Josh Poimboeuf <jpoimboe@redhat.com>,
        David Woodhouse <dwmw@amazon.co.uk>,
        Andi Kleen <ak@linux.intel.com>,
        "dave.hansen@intel.com" <dave.hansen@intel.com>,
        Casey Schaufler <casey.schaufler@intel.com>,
        "Mallick, Asit K" <asit.k.mallick@intel.com>,
        "Van De Ven, Arjan" <arjan@linux.intel.com>,
        "jcm@redhat.com" <jcm@redhat.com>,
        "longman9394@gmail.com" <longman9394@gmail.com>,
        Greg KH <gregkh@linuxfoundation.org>,
        "david.c.stewart@intel.com" <david.c.stewart@intel.com>,
        Kees Cook <keescook@chromium.org>
References: <20181125183328.318175777@linutronix.de>
 <20181125185006.051663132@linutronix.de>
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 <20181126204842.GC16136@redhat.com>
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From:   Tim Chen <tim.c.chen@linux.intel.com>
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Subject: Re: [patch V2 27/28] x86/speculation: Add seccomp Spectre v2 user
 space protection mode
Message-ID: <e96d423f-92d9-10fa-0b69-0b5ccc0ad2e0@linux.intel.com>
Date:   Mon, 26 Nov 2018 16:37:40 -0800
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Sender: linux-kernel-owner@vger.kernel.org
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On 11/26/2018 01:52 PM, Lendacky, Thomas wrote:
> On 11/26/2018 02:58 PM, Thomas Gleixner wrote:
>> On Mon, 26 Nov 2018, Andrea Arcangeli wrote:
>>
>>> Hello,
>>>
>>> On Sun, Nov 25, 2018 at 11:28:59PM +0100, Thomas Gleixner wrote:
>>>> Indeed. Just checked the documentation again, it's also not clear whether
>>>> IBPB is required if STIPB is in use.
>>>
>>> I tried to ask this question too earlier:
>>>
>>> https://lkml.kernel.org/r/20181119234528.GJ29258@redhat.com
>>>
>>> If the BTB mistraining in SECCOMP context with STIBP set in SPEC_CTRL,
>>> can still influence the hyperthreading sibling after STIBP is cleared,
>>> IBPB is needed before clearing STIBP. Otherwise it's not. Unless told
>>> otherwise, it'd be safe to assume IBPB is needed in such case.
>>
>> IBPB is still issued. I won't change that before we have clarification.
> 
> From an AMD standpoint, we recommend still issuing the IBPB.
> 

Yes, our Intel HW architect also recommends still issuing the IBPB.  We're now
getting approval for some additional explanations of STIBP.  Those additional
explanations should help clarify things.

Thanks.

Tim