Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp386902imu; Mon, 26 Nov 2018 23:45:03 -0800 (PST) X-Google-Smtp-Source: AFSGD/WP/5/4545z9o+vrHJe+oj3t8f0wq/Upi9ZXJR8ANPClnPfXqAnkvOmXJW7jGC50uE2s2ir X-Received: by 2002:a63:a112:: with SMTP id b18mr28383198pgf.440.1543304703577; Mon, 26 Nov 2018 23:45:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543304703; cv=none; d=google.com; s=arc-20160816; b=u58zK6R7K51NEBjcKQmNdJDpyB9bF1nWsfVI4gOlRd0lpMZMLzM8Ok+r/NTP5xb9z0 CUyg5JoXPXBLdMSNJ+dw2t3fDJBpfX2NOJVshvewLQvw5YnDw93vH1zp2ppgveE0vObc a6qSv1rDyi7+G/RFgHEnx/35snzRKnnUPx2tzJbq97tcHLdDXuq0XOnLR6XEkKaeY4T1 Y/p3N01IUs0Dgdfx6DOwfEUpwvSw5vPzo6IUlA/RUeH3LmmddFqRdldUKoCX4RT6sjOD IAeyA1r3YX0IyYslXVp4QLjJvvhBeeFDU9w7O2MsKyog5+CV/exq+Swl8I+sy19J6T9E bztQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=cYReYrg1z3cug5I4qFlmmlkV7lhOP3owGInx9gEjII4=; b=y75xyoCe5noFaCSIQdI5XsbhNY6t/uYt1qpnbPA8BcENvA7hT3AmIBYlrHj0nkFB+j 8Zp/HfZb7VlbCVj0sLJhbk+ltEEFO9cPjJ7iyio7lJKDLiOjdPNdi4fwOc0pfQK+Ui6B k/rpxRcsYa1tH+a3RpqNIEhcDRd/mgrnm+JEKCErHPZik8Qq4Hfga3tLX71UOwfxosLg 1OFkSifS/JlJPorg7BOMGFSREHBpnnSVWI4JdCNEmfm2Mopv5/l8IYhF9qk/QxJLC55r pUV5p2V5ZxhzeA2oxvC9/t9bNEGpLF9k1AAv3z42FeCKRPi+JRtPtb9LSeh6oYwJ0R1U NU6Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z71si2784098pgd.490.2018.11.26.23.44.47; Mon, 26 Nov 2018 23:45:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729208AbeK0Sk2 (ORCPT + 99 others); Tue, 27 Nov 2018 13:40:28 -0500 Received: from hermes.aosc.io ([199.195.250.187]:37346 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729143AbeK0Sk2 (ORCPT ); Tue, 27 Nov 2018 13:40:28 -0500 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 02DA611E7EF; Tue, 27 Nov 2018 07:43:24 +0000 (UTC) From: Icenowy Zheng To: Jernej Skrabec , Chen-Yu Tsai , Maxime Ripard , David Airlie , Rob Herring , Mark Rutland Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [PATCH 2/2] dt-bindings: gpu: add Allwinner H6 Mali Midgard binding Date: Tue, 27 Nov 2018 15:42:49 +0800 Message-Id: <20181127074249.15204-2-icenowy@aosc.io> In-Reply-To: <20181127074249.15204-1-icenowy@aosc.io> References: <20181127074249.15204-1-icenowy@aosc.io> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Allwinner H6 SoC uses a Mali T720 GPU, which is one of the GPUs in the Midgard GPU product line. Add binding for the H6 Mali Midgard GPU. Signed-off-by: Icenowy Zheng --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 02f870cd60e6..c897dd7be48f 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -18,6 +18,7 @@ Required properties: + "amlogic,meson-gxm-mali" + "rockchip,rk3288-mali" + "rockchip,rk3399-mali" + + "allwinner,sun50i-h6-mali" - reg : Physical base address of the device and length of the register area. @@ -44,6 +45,18 @@ Optional properties: for details. +Vendor-specific bindings +------------------------ + +The Mali GPU is integrated very differently from one SoC to +another. In order to accomodate those differences, you have the option +to specify one more vendor-specific compatible, among: + + - allwinner,sun50i-h6-mali + Required properties: + * resets: phandle to the reset line for the GPU + + Example for a Mali-T760: gpu@ffa30000 { -- 2.18.1