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received-spf: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: D1E0pKjB0BKbXqc2/FFUMfLmveUItiiVp0HxPoL/b/WO4LYy0adN4GciDOcrv5PprN0Pe76bkuEuYYz7ALa3iZYdndoRvW/448+TanaIC+vXBRomN18MMUdPzcYfnKIx2sthwny7F3hr0UBgGHQE7Vys2NZ5pg90jHfTp4Fip6t3KYvGLv5xyXAjAtyq1Wj6E59IotBVKqLiS3494a/T6GZ6h97qwzntnJR0elxgabbJmQvyuy6G1mleupgmnEZ14oqxP+fQLl0mk5XcmgjQRCzX33SefgtGk5BPaNfe1Sljw7vZdZS+RJ9AdNqVgOogFmozFnsFGfoI1dd8dCGN137s3B9R1v4u1esfUk8V00o= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-Network-Message-Id: 24f642b2-cdf1-4188-1a41-08d654648991 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Nov 2018 12:33:30.6579 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR07MB4215 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi James, On Fri, Aug 24, 2018 at 11:44:59AM +0100, James Morse wrote: > Hi folks, >=20 > ARM have some upcoming CPU features that are similar to Intel RDT. Resctr= l > is the defacto ABI for this sort of thing, but it lives under arch/x86. >=20 > To get existing software working, we need to make resctrl work with arm64= . > This series is the first chunk of that. The aim is to move the filesystem= /ABI > parts into /fs/resctrl, and implement a second arch backend. >=20 >=20 > What are the ARM features? > Future ARM SoCs may have a feature called MPAM: Memory Partitioning and > Monitoring. This is an umbrella term like RDT, and covers a range of cont= rols > (like CAT) and monitors (like MBM, CMT). >=20 > This series is almost all about CDP. MPAM has equivalent functionality, b= ut > it doesn't need enabling, and doesn't affect the available closids. (I'll > try and use Intel terms). MPAM expects the equivalent to IA32_PRQ_MSR to > be configured with an Instruction closid and a Data closid. These are the > same for no-CDP, and different otherwise. There is no need for them to be > adjacent. >=20 > To avoid emulating CDP in arm64's arch code, this series moves all the AB= I > parts of the CDP behaviour, (half the closid-space, each having two > configurations) into the filesystem parts of resctrl. These will eventual= ly > be moved to /fs/. >=20 > MPAMs control and monitor configuration is all memory mapped, the base > addresses are discovered via firmware tables, so we won't have a table of > possible resources that just need alloc_enabling. >=20 > Is this it? No... there are another two series of a similar size that > abstract the MBM/CMT overflow threads and avoid 'fs' code accessing thing= s > that have moved into the 'hw' arch specific struct. >=20 >=20 > I'm after feedback on the general approach taken here, bugs, as there are > certainly subtleties I've missed, and any strong-opinions on what should = be > arch-specific, and what shouldn't. >=20 > This series is based on v4.18, and can be retrieved from: > git://linux-arm.org/linux-jm.git -b mpam/resctrl_rework/rfc_1 Thank you a lot for this work on cache allocation. We are very interested in enabling CAT on Cavium / Marvell devices. Could you please share another two series you mentioned above? Do you have a working ARM64 CAT driver? It will much help us in our experimenting. Thanks in advance, Yury