Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp45957imu; Tue, 27 Nov 2018 08:50:46 -0800 (PST) X-Google-Smtp-Source: AFSGD/V9CR9oinY9OHCKp4OL6BxIUY62A0mKwM5z4ickzeb81YwPqCL4zZjUpGixgcqLqn5ujqPw X-Received: by 2002:a17:902:1e9:: with SMTP id b96mr33290076plb.150.1543337446245; Tue, 27 Nov 2018 08:50:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543337446; cv=none; d=google.com; s=arc-20160816; b=Nrs/6yOcc+cPdxo4s4N0VrXM5lHKQ5mhyP0X9fHHrXBrDtR4yJZ/bkVJODXTM6j6DA yb15DB3MDjMVi1YcCVB/Dl9u+eNav64/LWx70U41MlPCoBUQ8oYVLl2A++cSEQQoUpig +Ycr1X25GFDK8aDzZ9WnpQN/W9DpvdaSJYNfM3rkPL2p9moxrz+UYEpYJSa9b5epFV/a pJj/93MsHhC0GCWVFRQ5xQuhhSHDdjibwCEiKuXbxpCzGP56NYPgHvVpbuNedlRNyOFS ccweH9jBEY31h55mvAgzLoOaQZxO2wjns5o8wf0MFu9WKAtTUXkNXDIAbggoj7uy757a 1hOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from; bh=uemhtDjfaBFhk1ih0u6kcOPGKfl6RadLV1sI9jRXzuM=; b=voOFnuR2N6UL2ujHrPWKGpb8v2d2SjiIWLneYRkPVH+EYWvb2mMs8+1FecxnIvJQR7 Z8ggJwr4uO3EZZRSW9IZ+2ipkg7e278Y6EvqKFHhtZa2tgXJ+1R8VRxpkJHKHzPjMiCk sQDN2fvvAWQMV/jZio5soXH1ai59Cfi77+MPnY0ZXAdWleu1g+bM7lM4XBFlkFpmD0E6 m5jzTvZBedFTPVauqhSJ9ZE9o+wzpSg13epdYf4bINpCrDjO6jXg7Jme96Yg3dx3sBdd Xn9QFfpH96Xi8juCF2IvYzxG6OuAPxXtpegOrPb0sI1A7J+r6upqPWPZ/1HFl4K0LU9r bVWQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j24si4036911pgh.362.2018.11.27.08.49.51; Tue, 27 Nov 2018 08:50:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731351AbeK1DrT (ORCPT + 99 others); Tue, 27 Nov 2018 22:47:19 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:64607 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726729AbeK1DrS (ORCPT ); Tue, 27 Nov 2018 22:47:18 -0500 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id wARGdOjs008239; Tue, 27 Nov 2018 17:48:26 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2nxw9x1d12-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 27 Nov 2018 17:48:26 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 20FB6348; Tue, 27 Nov 2018 17:47:57 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id AB92F5330; Tue, 27 Nov 2018 16:48:25 +0000 (GMT) Received: from localhost (10.75.127.46) by SFHDAG5NODE3.st.com (10.75.127.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 27 Nov 2018 17:48:25 +0100 From: Fabrice Gasnier To: , , CC: , , , , , , , , Subject: [PATCH 0/3] mfd: syscon: Add optional clock support needed on stm32 Date: Tue, 27 Nov 2018 17:48:14 +0100 Message-ID: <1543337297-21873-1-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG1NODE1.st.com (10.75.127.1) To SFHDAG5NODE3.st.com (10.75.127.15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-11-27_14:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org STM32 syscfg registers are accessed using syscon. It needs syscfg clock to be enabled while accessing registers. This adds support for optional clock on syscon, and the relevant clock in stm32mp157 device tree. Fabrice Gasnier (3): dt-bindings: mfd: syscon: Add optional clock support mfd: syscon: Add optional clock support ARM: dts: stm32: Add clock on stm32mp157c syscfg Documentation/devicetree/bindings/mfd/syscon.txt | 1 + arch/arm/boot/dts/stm32mp157c.dtsi | 1 + drivers/mfd/syscon.c | 19 +++++++++++++++++++ 3 files changed, 21 insertions(+) -- 1.9.1