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From:   Stephane Eranian <eranian@google.com>
Date:   Tue, 27 Nov 2018 17:25:13 -0800
Message-ID: <CABPqkBQseMq2xnvw71VXT6F=ZR57L+HUAmQ_dZY356Et8NpxQg@mail.gmail.com>
Subject: Re: [REGRESSION] x86, perf: counter freezing breaks rr
To:     Andi Kleen <ak@linux.intel.com>
Cc:     Kyle Huey <me@kylehuey.com>, Peter Zijlstra <peterz@infradead.org>,
        "Liang, Kan" <kan.liang@linux.intel.com>,
        Ingo Molnar <mingo@kernel.org>, robert@ocallahan.org,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Arnaldo Carvalho de Melo <acme@redhat.com>,
        Jiri Olsa <jolsa@redhat.com>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Vince Weaver <vincent.weaver@maine.edu>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        LKML <linux-kernel@vger.kernel.org>
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On Tue, Nov 27, 2018 at 3:36 PM Andi Kleen <ak@linux.intel.com> wrote:
>
> > It does seem that FREEZE_PERFMON_ON_PMI (misnamed as it is) is of
> > rather limited use (or even negative, in our case) to a counter that's
> > already restricted to ring 3.
>
> It's much faster. The PMI cost goes down dramatically.
>
> I still the the right fix is to add an perf event opt-out and let it be
> used by rr.
>
>    V3 is without counter freezing.
>     V4 is with counter freezing.
>     The value is the average cost of the PMI handler.
>     (lower is better)
>
>     perf options    `           V3(ns) V4(ns)  delta
>     -c 100000                   1088   894     -18%
>     -g -c 100000                1862   1646    -12%
>     --call-graph lbr -c 100000  3649   3367    -8%
>     --c.g. dwarf -c 100000      2248   1982    -12%
>
Is that measured on the same machine, i.e., do you force V3 on Skylake?
All it does, I think, is save one wrmsr(GLOBAL_CTLR) on entry to the
PMU interrupt handler or am I missing something?
Or does it save two? The wrmsr(GLOBAL_CTRL) at the end to reactivate.

>
> -Andi
>