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From:   Leonard Crestez <leonard.crestez@nxp.com>
To:     Andrey Smirnov <andrew.smirnov@gmail.com>,
        Lucas Stach <l.stach@pengutronix.de>,
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        Aisheng DONG <aisheng.dong@nxp.com>,
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        Bjorn Helgaas <bhelgaas@google.com>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: Re: [PATCH 3/3] PCI: imx: Add support for i.MX8MQ
Thread-Topic: [PATCH 3/3] PCI: imx: Add support for i.MX8MQ
Thread-Index: AQHUfqElwnFd442790GkPu5+DDDqQQ==
Date:   Wed, 28 Nov 2018 10:55:42 +0000
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On 11/27/18 11:15 PM, Andrey Smirnov wrote:=0A=
> On Tue, Nov 27, 2018 at 2:46 AM Leonard Crestez <leonard.crestez@nxp.com>=
 wrote:=0A=
>> On 11/27/18 12:06 PM, Lucas Stach wrote:=0A=
>>> Am Montag, den 26.11.2018, 10:24 -0800 schrieb Andrey Smirnov:=0A=
>>>> On Tue, Nov 20, 2018 at 2:49 AM Leonard Crestez <leonard.crestez@nxp.c=
om> wrote:=0A=
>>>>> On Sat, 2018-11-17 at 10:12 -0800, Andrey Smirnov wrote:=0A=
>>>>>> @@ -921,7 +1004,28 @@ static int imx6_pcie_probe(struct platform_dev=
ice *pdev)=0A=
>>>>>> -     case IMX7D:=0A=
>>>>>> +     case IMX8MQ:=0A=
>>>>>> +             if (of_property_read_u32(node, "fsl,iomux-gpr1x",=0A=
>>>>>> +                                      &imx6_pcie->gpr1x)) {=0A=
>>>>>> +                     dev_err(dev, "Failed to get GPR1x address\n");=
=0A=
>>>>>> +                     return -EINVAL;=0A=
>>>>>> +             }=0A=
>>>>>=0A=
>>>>> This is for distinguishing multiple controllers on the SOC but other=
=0A=
>>>>> registers and bits might differ. Isn't it preferable to have a proper=
ty=0A=
>>>>> for controller id instead of adding many registers to DT?=0A=
>>>>=0A=
>>>> I liked encoding necessary info in DT directly slightly better than=0A=
>>>> encoding abstract ID and then decoding it further in the driver code.=
=0A=
>>>> OTOH, I am not really attached to that path. Lucas, can you comment on=
=0A=
>>>> this please?=0A=
=0A=
>>> Yes, after rereading the patch with this in mind I agree that having=0A=
>>> the GPR offset on DT directly is IMO the better approach than an=0A=
>>> abstract ID.=0A=
>>=0A=
>> But it's not a single offset, for example the device_type (EP/RC) has=0A=
>> bits for the two controllers side-by-side in GPR12.=0A=
>>=0A=
> =0A=
> Playing devil's advocate for a bit:=0A=
> =0A=
> More specifically, currently the following per-controller bits need to=0A=
> be configured:=0A=
> =0A=
> - Location of the "device type" field within GPR12=0A=
> - GPR register to use to control PCIn_CLKREQ_B_OVERRIDE_EN and=0A=
> PCIn_CLKREQ_B_OVERRIDE_EN (GPR14 vs GPR16)=0A=
> - Now that Philip spoke against PCIE_CTRL_APPS_CLK_REQ being exposed=0A=
> via reset controller driver, we need to know which SRC register to use=0A=
> to control that bit (SRC_PCIEPHY_RCR vs. SRC_PCIE2_RCR)=0A=
=0A=
I looked a bit through bindings and there some instances of syscon-$BLH =0A=
properties which include detailed offsets or bitmasks for $BLAH relative =
=0A=
to the target syscon node.=0A=
=0A=
If you're going the route of adding properties points to IOMUXC/SRC bits =
=0A=
it would sense to ensure that they're also usable on other SOCs, =0A=
otherwise you're just making 8mq more complicated. But that's hard.=0A=
=0A=
But I think it's easier to deal with such SOC-specific details behind a =0A=
compat string. Maybe the DT list has some opinion on this?=0A=
=0A=
I wonder if of_alias_get_id would be a reasonable way to distinguish =0A=
between pcie0 and pcie1 instead of adding an ctrl-id property?=0A=
=0A=
--=0A=
Regards,=0A=
Leonard=0A=