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[209.132.180.67]) by mx.google.com with ESMTP id s8si7824219pgl.503.2018.11.28.14.35.15; Wed, 28 Nov 2018 14:35:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=bPI5b4tI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727044AbeK2Jhk (ORCPT + 99 others); Thu, 29 Nov 2018 04:37:40 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:38771 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726414AbeK2Jhj (ORCPT ); Thu, 29 Nov 2018 04:37:39 -0500 Received: by mail-wm1-f65.google.com with SMTP id k198so275071wmd.3; Wed, 28 Nov 2018 14:34:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X2MJDswe0qbs6RG81mMPQ4p4MRYjzcSOeYYQ8FhXgr8=; b=bPI5b4tIqowdj0Ud4jLiRICip+blzwO95SDrV2KPUwtVblR7T3rA34/m0pY0cj0K7A UrUNQk81MeL7EchjqwTo/SvIyuDwXZweitxGJA8Xcg6JpOn2mqvXlgHYVokhYk45q0pk jSLP2Wp2U9MS+DlN2fQSGi4FyYwqPs9Ip5ZJ29yNpJBjsDE3I3uGE3rFNwbONdX/GWOj FGSz4AevULt8k2KjzygDU5E8qmJ/TAjjZp8cyh9poW7f82gWjg8ZuECfY8eAIaZd3L7y VJmJGiSelKZKw+Uz2jFs36/XbsUnoQyBSNLu6y3xVrQoGHzjAk90F0TuR/LPbfZ9nOj6 mStg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=X2MJDswe0qbs6RG81mMPQ4p4MRYjzcSOeYYQ8FhXgr8=; b=dt7ND7jGMCRkOwJ+rInFd90ktTChguDrN6USCxlsLm+TzhWyTaLCjMybgLwOZmFfgy /9syD7fHBEIfzWGUXA69yqfaiLHrXhQ4VHRb0Bjor7Avf7XboLGCP0sVm43suma2Feyw RFAV5RawFA0JEq0p1ewTSkBvPcTvKU+LDwFCsoFYGMBF+1xyrmy+mo2QvPm8yhWjqYoQ 6e3DLEcwievIiXAsCgzLcBIlP+TEn0ZmfzUtXOBhB2Ehv6LhAgYpU2sKwq5JTh0WS3Ue WosbzZ08HzDtlM3l7iQc5lE5Pd7y2WME9W9euPKm6Aimlr6zJNpdog+VxFPR3Y7JwEpJ G7aw== X-Gm-Message-State: AA+aEWaGMMR7tg05uHjHHv6W0P5gAzTSA/dmqdbL5WBZ7yKIGZtkxDzX MGPLY5NsTtWhhi3N/FRTEPWsznQdrPg= X-Received: by 2002:a1c:4d12:: with SMTP id o18mr4572266wmh.92.1543444466730; Wed, 28 Nov 2018 14:34:26 -0800 (PST) Received: from ThinkPad.home ([185.219.177.239]) by smtp.gmail.com with ESMTPSA id g198sm180244wmd.23.2018.11.28.14.34.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Nov 2018 14:34:26 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v5 09/17] clocksource: sun4i: add a compatible for suniv Date: Thu, 29 Nov 2018 01:33:19 +0300 Message-Id: <274bfd74bf3817065b6e5bdc733edecc520449b6.1543443475.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The suniv (new F-series) chip has a timer with less functionality than the A10 timer, e.g. it has only 3 channels. Add a new compatible for it. As we didn't use the extra channels on A10 either now, the code needn't to be changed. The suniv chip is based on ARM926EJ-S CPU, thus it has no architecture timer. Register sun4i_timer as sched_clock on it. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Acked-by: Daniel Lezcano --- drivers/clocksource/sun4i_timer.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c index 6e0180a..65f38f6 100644 --- a/drivers/clocksource/sun4i_timer.c +++ b/drivers/clocksource/sun4i_timer.c @@ -186,7 +186,8 @@ static int __init sun4i_timer_init(struct device_node *node) */ if (of_machine_is_compatible("allwinner,sun4i-a10") || of_machine_is_compatible("allwinner,sun5i-a13") || - of_machine_is_compatible("allwinner,sun5i-a10s")) + of_machine_is_compatible("allwinner,sun5i-a10s") || + of_machine_is_compatible("allwinner,suniv-f1c100s")) sched_clock_register(sun4i_timer_sched_read, 32, timer_of_rate(&to)); @@ -218,3 +219,5 @@ static int __init sun4i_timer_init(struct device_node *node) } TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer", sun4i_timer_init); +TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer", + sun4i_timer_init); -- 2.7.4