Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp1749242imu; Wed, 28 Nov 2018 14:36:11 -0800 (PST) X-Google-Smtp-Source: AJdET5f3I3elbGsPYr6ARojvSjmFDwa2OO+JhC7qDAxxEtdk64m0+0kiZjQA3QGfTooumBYi4fNi X-Received: by 2002:a62:e201:: with SMTP id a1mr38541588pfi.75.1543444571370; Wed, 28 Nov 2018 14:36:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543444571; cv=none; d=google.com; s=arc-20160816; b=oljlooP6njCG1rYVhzGQbRUZ2Y8F0eESQVEat/saZIjfrQ2780tCtqBumNt0soq4Zx Ovrr7Ldd02A16IfyQclMdIv38TRC0E8MfI8D2pXuF0amVja+nfqYwccvRcz/VdE+b6vD MD5ei69TrTlVYG17UFlvnlpkNidgbNJHnwoNm0a+BeqLEYl6g3CUlNvQps5ceZbQtD64 rerOe1v5bhxLzYG4pBaBc/lPX1KA81rCyXYNBnticTMA2eA+IKE9D2f3tcntThjELuvZ +3/A1hnrxXtatIpCTSsaPtlPWtfggYNHU4WYHbGslSCc/6aR+j0Qnwdgkiil3+1Q7pTZ 8emw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=9WG2eU/ejG4wAWToKoueA27/6ygzN1rLZLWAo8LIhNE=; b=S/LSD9/g4FGbpeO8wTWVBEZuD5HB2DnEVfeSCt+sqMTcs/Frn9FLVLKLhKyZqsIfwf Wosdythrt0WvU3nIsiLt8rYA2mxy3zPftb872xhPWmKdFBrUIfRT5WhTgClzw8/Iy62z lpB589uusg7D9jg6Elkew7Va98oaoK+nppHXn8z5mX/VV+oAfCdBTpYgKAByKhDb3PNp zwuFnYrV9iN9bvts0vPlwYQHVIQqjyGsTd01u6Lw3bUhdl8GnFXyoRAN95XQfY4GpN0K Nxor/oBy2Jyi6KETGbxWW6Qxoa+JvYHD9ckh69gVy7QSQVTBbkoV+0WBX54pEfY5sjYm gSAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=ga3BkypM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c8si9883851pfe.243.2018.11.28.14.35.56; Wed, 28 Nov 2018 14:36:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=ga3BkypM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727333AbeK2Jhy (ORCPT + 99 others); Thu, 29 Nov 2018 04:37:54 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:46722 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727166AbeK2Jhw (ORCPT ); Thu, 29 Nov 2018 04:37:52 -0500 Received: by mail-wr1-f65.google.com with SMTP id l9so27906140wrt.13; Wed, 28 Nov 2018 14:34:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9WG2eU/ejG4wAWToKoueA27/6ygzN1rLZLWAo8LIhNE=; b=ga3BkypMafnIrlIbTkOz7SkxXzmYMDMUlEcgr2JTXWZhpvI+aG8kd83AUIFgVSjeXA ellD4QPs7Ssv/URymLaizJqg+caslTJ8a7wDtWL5pbC75wv49SytulWzkmWTD2JN6BwS Jj1ZIz/up5rwjkXLQnfxtSUcqRruoFS0VJDBbd3RclYdNySiPSjQsQ24TBrLo5AQQspg 4hE4CH7vvSeL0aIgcqY1OpEczZaIg/jffchAUGeVnMVHq5mcgrE7IQcYtPfXG1ktPKZ8 YBgLeM902M7dW1KzzXL5V5doK9FibPz49T/TAQ+idiMBnnoQNx73yUv7vT2uSt8+GQyP x4gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9WG2eU/ejG4wAWToKoueA27/6ygzN1rLZLWAo8LIhNE=; b=VyAAX6BYvr2ya9czUV3OmXXAfce32XbbMGQqsypV8++qXt0M/e2LCSDp6mFMDKA3k2 KRyvi8QyowfeQWiMkrmjNVH9rMwHYti0+ZKPQQiPtjlIj1p6Vm9GWNtxUR3zJ5+zCpei i+wE0agKQRfXeehrEcTowoB9z/lqUkr2Kt3kae4YjXbMe9w5LmX1UYJ2sTIUJEinqfwC GXhCFUV+4dhb0T4XWJ5BwyOgGlqB/C3fk3JZ6SScRPSrbXb9Kd8HieZhveiFmX/P7ZiK d4AfFTT1Dx//ur96HY4w/1asT1Vh1paJKp7Jj8NdtqLdc6P23AsQGjsh7Kskx0ZKA7Up EweQ== X-Gm-Message-State: AA+aEWbIrDDwOeX9u/TTeJyhxIe/1Xw1LLJMdmg8rdeO5jr5xcTr7l7e UPPyxfL4IoHFrB9QVdzSzjkVVjt+0u8= X-Received: by 2002:adf:f1c2:: with SMTP id z2mr34191114wro.218.1543444479105; Wed, 28 Nov 2018 14:34:39 -0800 (PST) Received: from ThinkPad.home ([185.219.177.239]) by smtp.gmail.com with ESMTPSA id g198sm180244wmd.23.2018.11.28.14.34.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Nov 2018 14:34:38 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [PATCH v5 16/17] ARM: dts: suniv: add initial DTSI file for F1C100s Date: Thu, 29 Nov 2018 01:33:26 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org F1C100s is one product with the suniv die, which has a 32MiB co-packaged DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a initial DTSI for it. Signed-off-by: Mesih Kilinc --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 147 +++++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi new file mode 100644 index 0000000..aff5f90 --- /dev/null +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2018 Icenowy Zheng + * Copyright 2018 Mesih Kilinc + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + clocks { + osc24M: clk-24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: clk-32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + cpus { + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram-controller@1c00000 { + compatible = "allwinner,suniv-f1c100s-system-control", + "allwinner,sun4i-a10-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_d: sram@10000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0 { + compatible = "allwinner,suniv-f1c100s-sram-d", + "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,suniv-f1c100s-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + intc: interrupt-controller@1c20400 { + compatible = "allwinner,suniv-f1c100s-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,suniv-f1c100s-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <38>, <39>, <40>; + clocks = <&ccu 37>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + uart0_pe_pins: uart0-pe-pins { + pins = "PE0", "PE1"; + function = "uart0"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,suniv-f1c100s-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <13>; + clocks = <&osc24M>; + }; + + wdt: watchdog@1c20ca0 { + compatible = "allwinner,suniv-f1c100s-wdt", + "allwinner,sun4i-a10-wdt"; + reg = <0x01c20ca0 0x20>; + }; + + uart0: serial@1c25000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25000 0x400>; + interrupts = <1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu 38>; + resets = <&ccu 24>; + status = "disabled"; + }; + + uart1: serial@1c25400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu 39>; + resets = <&ccu 25>; + status = "disabled"; + }; + + uart2: serial@1c25800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu 40>; + resets = <&ccu 26>; + status = "disabled"; + }; + }; +}; -- 2.7.4