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[209.132.180.67]) by mx.google.com with ESMTP id e89si1753517plb.401.2018.11.29.02.12.05; Thu, 29 Nov 2018 02:12:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=o2Bf06yR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728007AbeK2VOx (ORCPT + 99 others); Thu, 29 Nov 2018 16:14:53 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:17960 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726621AbeK2VOw (ORCPT ); Thu, 29 Nov 2018 16:14:52 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 29 Nov 2018 02:10:05 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 29 Nov 2018 02:10:03 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 29 Nov 2018 02:10:03 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 29 Nov 2018 10:10:03 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 29 Nov 2018 10:10:02 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 29 Nov 2018 10:10:02 +0000 Received: from niwei-ubuntu.nvidia.com (Not Verified[10.19.225.182]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 29 Nov 2018 02:10:01 -0800 From: Wei Ni To: , , CC: , , , , Wei Ni Subject: [PATCH v4 3/3] thermal: tegra: parse sensor id before sensor register Date: Thu, 29 Nov 2018 18:09:43 +0800 Message-ID: <1543486183-2868-4-git-send-email-wni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1543486183-2868-1-git-send-email-wni@nvidia.com> References: <1543486183-2868-1-git-send-email-wni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543486205; bh=1vLS67MRV1cSQ3NTjEgx5+FLaSxsY9XT5a4ufZClFco=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=o2Bf06yRjGx8jDzso5+SKHvBIi3U1y7Gbtp4L9xizFIvKksu3WNdXylNnAgQkBohF FTNqwkav1NHMqZTWf4tD5wCh6wl+Ma7kn+2J1vRcDcIgzMZFwHDkLTOhT3+/TiRwnl 2xA3b/5dXGXAqJ/eNBCrDykvNSnaVee49wvHMqcx3CwBDR7dmA8NUsaaMmCTbX13G1 nolpuo5Frn2BCez1ucl3HCcCeQkiXE6nyizE0FWclnvApT3+Y9uhNm+CtuFaRnQrEV pzhKKKN7PHWxIYW9bhKH209/m9HgkZ5hNVYxYl9CVwDGdCeC+ejMRGQQ20+NM4Je3r JY7wHmo106eLg== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since different platforms may not support all 4 sensors, so the sensor registration may be failed. Add codes to parse dt to find sensor id which need to be registered. So that the registration can be successful on all platform. Signed-off-by: Wei Ni --- drivers/thermal/tegra/soctherm.c | 46 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c index 375cadbc24cd..bdc660f2794a 100644 --- a/drivers/thermal/tegra/soctherm.c +++ b/drivers/thermal/tegra/soctherm.c @@ -1224,6 +1224,42 @@ static void soctherm_init(struct platform_device *pdev) tegra_soctherm_throttle(&pdev->dev); } +static bool tegra_soctherm_find_sensor_id(unsigned int sensor_id) +{ + bool ret = false; + struct of_phandle_args sensor_specs; + struct device_node *np, *sensor_np; + + np = of_find_node_by_name(NULL, "thermal-zones"); + if (!np) + return ret; + + sensor_np = of_get_next_child(np, NULL); + for_each_available_child_of_node(np, sensor_np) { + if (of_parse_phandle_with_args(sensor_np, "thermal-sensors", + "#thermal-sensor-cells", + 0, &sensor_specs)) + continue; + + if (sensor_specs.args_count != 1) { + WARN(sensor_specs.args_count != 1, + "%s: wrong cells in sensor specifier %d\n", + sensor_specs.np->name, sensor_specs.args_count); + continue; + } + + if (sensor_specs.args[0] == sensor_id) { + ret = true; + break; + } + } + + of_node_put(np); + of_node_put(sensor_np); + + return ret; +} + static const struct of_device_id tegra_soctherm_of_match[] = { #ifdef CONFIG_ARCH_TEGRA_124_SOC { @@ -1365,13 +1401,16 @@ static int tegra_soctherm_probe(struct platform_device *pdev) zone->sg = soc->ttgs[i]; zone->ts = tegra; + if (!tegra_soctherm_find_sensor_id(soc->ttgs[i]->id)) + continue; + z = devm_thermal_zone_of_sensor_register(&pdev->dev, soc->ttgs[i]->id, zone, &tegra_of_thermal_ops); if (IS_ERR(z)) { err = PTR_ERR(z); - dev_err(&pdev->dev, "failed to register sensor: %d\n", - err); + dev_err(&pdev->dev, "failed to register sensor %s: %d\n", + soc->ttgs[i]->name, err); goto disable_clocks; } @@ -1434,6 +1473,9 @@ static int __maybe_unused soctherm_resume(struct device *dev) struct thermal_zone_device *tz; tz = tegra->thermctl_tzs[soc->ttgs[i]->id]; + if (!tz) + continue; + err = tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz); if (err) { dev_err(&pdev->dev, -- 2.7.4