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[209.132.180.67]) by mx.google.com with ESMTP id x8si2029068pll.187.2018.11.29.05.44.27; Thu, 29 Nov 2018 05:44:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728333AbeK3Arl (ORCPT + 99 others); Thu, 29 Nov 2018 19:47:41 -0500 Received: from mail-sh2.amlogic.com ([58.32.228.45]:19505 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728085AbeK3Arl (ORCPT ); Thu, 29 Nov 2018 19:47:41 -0500 Received: from droid15-sz.amlogic.com (10.28.8.25) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Thu, 29 Nov 2018 21:42:20 +0800 From: Jian Hu To: Jerome Brunet , Neil Armstrong CC: Jian Hu , Kevin Hilman , Carlo Caione , Rob Herring , Martin Blumenstingl , Michael Turquette , Stephen Boyd , Yixun Lan , Qiufang Dai , Jianxin Pan , , , , , Subject: [PATCH v5 0/2] clk: meson-g12a: Add EE clock controller driver Date: Thu, 29 Nov 2018 21:41:55 +0800 Message-ID: <1543498917-98605-1-git-send-email-jian.hu@amlogic.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.28.8.25] Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Changes since v4 at[5] -add bypass clock "g12a_ee_core" from DT -fix Kconfig description -change g12a_mpll0_div/g12a_mpll1_div/g12a_mpll2_div/g12a_mpll3_div clock's parent name as fixed_pll_dco -drop CLK_SET_RATE_PARENT flag for pll clock -drop CLK_GET_RATE_NOCACHE flag for pll_dco clock -delete usless note -enable G12A clock driver Changes since v3 at[4] -add fixed clocks clk_regmap definition Changes since v2 at[2] -fix fixed clocks's descriptions -fix alignment -add enable bit for plls base on [3] patches -add fixed clock gate bit Changes since v1 at[1] -fix typo of 'Everything'. -change the word 'AmLogic' to 'Amlogic' -squash patch 1 and 2. -delete usless message of "Trying obsolete regs". -delete the empty line in include/dt-bindings/clock/g12a-clkc.h. -rebase on top of the "next/drivers" branch, and add g12a clock patch. -add CLK_MUX_ROUND_CLOSEST for g12a_sd_emmc_b_clk0_sel and g12a_sd_emmc_c_clk0_sel. [1]https://lkml.kernel.org/r/1531133549-25806-2-git-send-email-jian.hu@amlogic.com [2]https://lkml.kernel.org/r/1531728707-192230-2-git-send-email-jian.hu@amlogic.com [3]https://lkml.kernel.org/r/20180717095617.12240-1-jbrunet@baylibre.com [4]https://lkml.kernel.org/r/1533890858-113020-1-git-send-email-jian.hu@amlogic.com [5]https://lkml.kernel.org/r/1541511349-121152-1-git-send-email-jian.hu@amlogic.com Jian Hu (2): dt-bindings: clk: meson-g12a: Add G12A EE Clock Bindings clk: meson-g12a: Add EE Clock controller driver .../bindings/clock/amlogic,gxbb-clkc.txt | 1 + arch/arm64/Kconfig.platforms | 1 + drivers/clk/meson/Kconfig | 8 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/g12a.c | 1185 ++++++++++++++++++++ drivers/clk/meson/g12a.h | 130 +++ include/dt-bindings/clock/g12a-clkc.h | 93 ++ 7 files changed, 1419 insertions(+) create mode 100644 drivers/clk/meson/g12a.c create mode 100644 drivers/clk/meson/g12a.h create mode 100644 include/dt-bindings/clock/g12a-clkc.h -- 1.9.1