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[209.132.180.67]) by mx.google.com with ESMTP id q1-v6si2578446plb.14.2018.11.29.08.28.44; Thu, 29 Nov 2018 08:29:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729044AbeK3DdW (ORCPT + 99 others); Thu, 29 Nov 2018 22:33:22 -0500 Received: from foss.arm.com ([217.140.101.70]:38622 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728562AbeK3DdW (ORCPT ); Thu, 29 Nov 2018 22:33:22 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 215C1A78; Thu, 29 Nov 2018 08:27:27 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 305293F59C; Thu, 29 Nov 2018 08:27:25 -0800 (PST) Date: Thu, 29 Nov 2018 16:27:22 +0000 From: Mark Rutland To: Julien Thierry Cc: linux-arm-kernel@lists.infradead.org, daniel.thompson@linaro.org, marc.zyngier@arm.com, catalin.marinas@arm.com, Suzuki K Poulose , will.deacon@arm.com, linux-kernel@vger.kernel.org, christoffer.dall@arm.com, james.morse@arm.com, joel@joelfernandes.org Subject: Re: [PATCH v6 02/24] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Message-ID: <20181129162722.s2ee2mdteli7jdir@lakrids.cambridge.arm.com> References: <1542023835-21446-1-git-send-email-julien.thierry@arm.com> <1542023835-21446-3-git-send-email-julien.thierry@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1542023835-21446-3-git-send-email-julien.thierry@arm.com> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 12, 2018 at 11:56:53AM +0000, Julien Thierry wrote: > It is not supported to have some CPUs using GICv3 sysreg CPU interface > while some others do not. > > Once ICC_SRE_EL1.SRE is set on a CPU, the bit cannot be cleared. Since > matching this feature require setting ICC_SRE_EL1.SRE, it cannot be > turned off if found on a CPU. > > Set the feature as STRICT_BOOT, if boot CPU has it, all other CPUs are > required to have it. > > Signed-off-by: Julien Thierry > Suggested-by: Daniel Thompson > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Suzuki K Poulose > Cc: Marc Zyngier Makes sense. Reviewed-by: Mark Rutland Mark. > --- > arch/arm64/kernel/cpufeature.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index af50064..03a9d96 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1149,7 +1149,7 @@ static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) > { > .desc = "GIC system register CPU interface", > .capability = ARM64_HAS_SYSREG_GIC_CPUIF, > - .type = ARM64_CPUCAP_SYSTEM_FEATURE, > + .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, > .matches = has_useable_gicv3_cpuif, > .sys_reg = SYS_ID_AA64PFR0_EL1, > .field_pos = ID_AA64PFR0_GIC_SHIFT, > -- > 1.9.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel