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Date:   Thu, 29 Nov 2018 16:32:37 +0000
From:   Mark Rutland <mark.rutland@arm.com>
To:     Julien Thierry <julien.thierry@arm.com>
Cc:     linux-arm-kernel@lists.infradead.org, daniel.thompson@linaro.org,
        marc.zyngier@arm.com, catalin.marinas@arm.com, will.deacon@arm.com,
        linux-kernel@vger.kernel.org, christoffer.dall@arm.com,
        james.morse@arm.com, joel@joelfernandes.org,
        Russell King <linux@armlinux.org.uk>
Subject: Re: [PATCH v6 04/24] arm/arm64: gic-v3: Add PMR and RPR accessors
Message-ID: <20181129163237.dyppwn5ipkehv527@lakrids.cambridge.arm.com>
References: <1542023835-21446-1-git-send-email-julien.thierry@arm.com>
 <1542023835-21446-5-git-send-email-julien.thierry@arm.com>
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On Mon, Nov 12, 2018 at 11:56:55AM +0000, Julien Thierry wrote:
> Add helper functions to access system registers related to interrupt
> priorities: PMR and RPR.
> 
> Signed-off-by: Julien Thierry <julien.thierry@arm.com>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>

The AArch32 ICC_RPR encoding looks right per ARM DDI 0487D.a table G7-3,
and the rest looks sane to me.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>

Mark.

> ---
>  arch/arm/include/asm/arch_gicv3.h   | 16 ++++++++++++++++
>  arch/arm64/include/asm/arch_gicv3.h | 15 +++++++++++++++
>  2 files changed, 31 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
> index 0bd5307..bef0b5d 100644
> --- a/arch/arm/include/asm/arch_gicv3.h
> +++ b/arch/arm/include/asm/arch_gicv3.h
> @@ -34,6 +34,7 @@
>  #define ICC_SRE				__ACCESS_CP15(c12, 0, c12, 5)
>  #define ICC_IGRPEN1			__ACCESS_CP15(c12, 0, c12, 7)
>  #define ICC_BPR1			__ACCESS_CP15(c12, 0, c12, 3)
> +#define ICC_RPR				__ACCESS_CP15(c12, 0, c11, 3)
>  
>  #define __ICC_AP0Rx(x)			__ACCESS_CP15(c12, 0, c8, 4 | x)
>  #define ICC_AP0R0			__ICC_AP0Rx(0)
> @@ -245,6 +246,21 @@ static inline void gic_write_bpr1(u32 val)
>  	write_sysreg(val, ICC_BPR1);
>  }
>  
> +static inline u32 gic_read_pmr(void)
> +{
> +	return read_sysreg(ICC_PMR);
> +}
> +
> +static inline void gic_write_pmr(u32 val)
> +{
> +	write_sysreg(val, ICC_PMR);
> +}
> +
> +static inline u32 gic_read_rpr(void)
> +{
> +	return read_sysreg(ICC_RPR);
> +}
> +
>  /*
>   * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
>   * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
> diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
> index e278f94..37193e2 100644
> --- a/arch/arm64/include/asm/arch_gicv3.h
> +++ b/arch/arm64/include/asm/arch_gicv3.h
> @@ -114,6 +114,21 @@ static inline void gic_write_bpr1(u32 val)
>  	write_sysreg_s(val, SYS_ICC_BPR1_EL1);
>  }
>  
> +static inline u32 gic_read_pmr(void)
> +{
> +	return read_sysreg_s(SYS_ICC_PMR_EL1);
> +}
> +
> +static inline void gic_write_pmr(u32 val)
> +{
> +	write_sysreg_s(val, SYS_ICC_PMR_EL1);
> +}
> +
> +static inline u32 gic_read_rpr(void)
> +{
> +	return read_sysreg_s(SYS_ICC_RPR_EL1);
> +}
> +
>  #define gic_read_typer(c)		readq_relaxed(c)
>  #define gic_write_irouter(v, c)		writeq_relaxed(v, c)
>  #define gic_read_lpir(c)		readq_relaxed(c)
> -- 
> 1.9.1
> 
> 
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