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[209.132.180.67]) by mx.google.com with ESMTP id n28si2888486pfb.88.2018.11.29.10.59.01; Thu, 29 Nov 2018 10:59:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=R9SdpF++; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726585AbeK3GEN (ORCPT + 99 others); Fri, 30 Nov 2018 01:04:13 -0500 Received: from mail-io1-f65.google.com ([209.85.166.65]:40745 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725871AbeK3GEN (ORCPT ); Fri, 30 Nov 2018 01:04:13 -0500 Received: by mail-io1-f65.google.com with SMTP id n9so2455374ioh.7; Thu, 29 Nov 2018 10:57:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=lyy5yvTAUOmlEPj+xK+uWoEqiMsQzkVUDFwnxbzT9ZM=; b=R9SdpF++3J5wNrSgIIiOZH57y04E765lRhzJu/kQqrptWQC3+2C/YrjQ1ypCdoPswF tlnji4OlO5GOZ45I1+STjJxPErj+9EuvYC2IELaUiWir0z2vjKLPvor1wopKMk0tcnEx DcWVheElQWGPXrUAc22u2TNtg+GjrjSLcDqK6DEYb36EeEdyqLs8upIDMWaaAXZ4ItdU eISX637c0y5HKmNHjq6TODkxZwSkHNWsNqcFYB9IkOmnrDGqjcV686NZ2FlA3h1V7FCO EFDXdH7fAk5vQRvQKrXCU17VHHZ0Sim/kQAYTILnhEdLrhmHMZ/TIo/gvDkKvNen8HLB k6Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=lyy5yvTAUOmlEPj+xK+uWoEqiMsQzkVUDFwnxbzT9ZM=; b=hjIPG39UybShMAEZQK/xdHcgt/Cf3zQPFcCXSq+nfM4prYiB8DkYHodB7cawBLZvg/ 9KkEJxtJfOsQLHPj+VVeoEMdnMK9hoZnxiVbY3PJDTu9BUriL5Q/LjjZ1TdY58r2TSXd hlaWSGBSjYvCEh3dnYkiLrDCmz0THro1KEfDxb51VPQD1vybhi7oPI/V/AyV9vLKnk9L 7FL1w/Eap7Z0qAdIESFOZQdCpAfv3FiMVNjL0N2rH7DcJS8eCG4jejMwHW/rLbSNykko Nk4JEEdIyBX2IshXe3Yeuv3amFUy+MqbGGjL1QqdbcrjBW0k5Fac9rTzuikYZhowtybL RjVw== X-Gm-Message-State: AA+aEWYQ40/wJbstcAOl9lZs+rHTTTkOFSaoDMYee5gd2Ji2HM9bwvnn qAC/AmLbEtJU7Yc2nhezMNyt88s/INrYlZ1kKOM= X-Received: by 2002:a6b:fc05:: with SMTP id r5mr2207832ioh.129.1543517869444; Thu, 29 Nov 2018 10:57:49 -0800 (PST) MIME-Version: 1.0 References: <20181129140315.28476-1-vivek.gautam@codeaurora.org> <20181129141429.GA22638@lst.de> <20181129155758.GC26537@lst.de> <20181129162807.GL21184@phenom.ffwll.local> <20181129165715.GA27786@lst.de> In-Reply-To: From: Rob Clark Date: Thu, 29 Nov 2018 13:57:38 -0500 Message-ID: Subject: Re: [PATCH v3 1/1] drm: msm: Replace dma_map_sg with dma_sync_sg* To: Tomasz Figa Cc: Daniel Vetter , hch@lst.de, David Airlie , linux-arm-msm , Linux Kernel Mailing List , dri-devel , Sean Paul , Vivek Gautam , freedreno , Robin Murphy , Marek Szyprowski Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 29, 2018 at 12:24 PM Tomasz Figa wrote: > > [CC Marek] > > On Thu, Nov 29, 2018 at 9:09 AM Daniel Vetter wrote: > > > > On Thu, Nov 29, 2018 at 5:57 PM Christoph Hellwig wrote: > > > > > > Note that one thing I'd like to avoid is exposing these funtions directly > > > to drivers, as that will get us into all kinds of abuses. > > > > What kind of abuse do you expect? It could very well be that gpu folks > > call that "standard use case" ... At least on x86 with the i915 driver > > we pretty much rely on architectural guarantees for how cache flushes > > work very much. Down to userspace doing the cache flushing for > > mappings the kernel has set up. > > i915 is a very specific case of a fully contained, > architecture-specific hardware subsystem, where you can just hardcode > all integration details inside the driver, because nobody else would > care. > > In ARM world, you can have the same IP blocks licensed by multiple SoC > vendors with different integration details and that often includes the > option of coherency. fwiw, I believe all the GPU IP blocks that are used across multiple SoCs have their own GPU MMU (potentially in addition to an iommu?). So the dma-api is a much better fit for them.. drm/msm is a lot closer to drm/i915 scenario, so I don't so much care if the solution to our unique problem isn't something that would work for other drivers ;-) BR, -R