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[209.85.219.176]) by smtp.gmail.com with ESMTPSA id i21sm3711749ywg.5.2018.11.29.16.24.12 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Nov 2018 16:24:12 -0800 (PST) Received: by mail-yb1-f176.google.com with SMTP id h187-v6so1529423ybg.10 for ; Thu, 29 Nov 2018 16:24:12 -0800 (PST) X-Received: by 2002:a25:618a:: with SMTP id v132-v6mr3570547ybb.293.1543537451720; Thu, 29 Nov 2018 16:24:11 -0800 (PST) MIME-Version: 1.0 References: <20181129140315.28476-1-vivek.gautam@codeaurora.org> <20181129141429.GA22638@lst.de> <20181129155418.GB26537@lst.de> <20181129194029.GE17663@jcrouse-lnx.qualcomm.com> <06747338-b0fb-eef6-634a-0641e81ed3c1@arm.com> In-Reply-To: <06747338-b0fb-eef6-634a-0641e81ed3c1@arm.com> From: Tomasz Figa Date: Thu, 29 Nov 2018 16:23:59 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 1/1] drm: msm: Replace dma_map_sg with dma_sync_sg* To: Robin Murphy Cc: Rob Clark , Christoph Hellwig , Vivek Gautam , David Airlie , dri-devel , Linux Kernel Mailing List , freedreno , Archit Taneja , linux-arm-msm , Sean Paul Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 29, 2018 at 12:03 PM Robin Murphy wrote: > > On 29/11/2018 19:57, Tomasz Figa wrote: > > On Thu, Nov 29, 2018 at 11:40 AM Jordan Crouse wrote: > >> > >> On Thu, Nov 29, 2018 at 01:48:15PM -0500, Rob Clark wrote: > >>> On Thu, Nov 29, 2018 at 10:54 AM Christoph Hellwig wrote: > >>>> > >>>> On Thu, Nov 29, 2018 at 09:42:50AM -0500, Rob Clark wrote: > >>>>> Maybe the thing we need to do is just implement a blacklist of > >>>>> compatible strings for devices which should skip the automatic > >>>>> iommu/dma hookup. Maybe a bit ugly, but it would also solve a problem > >>>>> preventing us from enabling per-process pagetables for a5xx (where we > >>>>> need to control the domain/context-bank that is allocated by the dma > >>>>> api). > >>>> > >>>> You can detach from the dma map attachment using arm_iommu_detach_device, > >>>> which a few drm drivers do, but I don't think this is the problem. > >>> > >>> I think even with detach, we wouldn't end up with the context-bank > >>> that the gpu firmware was hard-coded to expect, and so it would > >>> overwrite the incorrect page table address register. (I could be > >>> mis-remembering that, Jordan spent more time looking at that. But it > >>> was something along those lines.) > >> > >> Right - basically the DMA domain steals context bank 0 and the GPU is hard coded > >> to use that context bank for pagetable switching. > >> > >> I believe the Tegra guys also had a similar problem with a hard coded context > >> bank. > > AIUI, they don't need a specific hardware context, they just need to > know which one they're actually using, which the domain abstraction hides. > > > Wait, if we detach the GPU/display struct device from the default > > domain and attach it to a newly allocated domain, wouldn't the newly > > allocated domain use the context bank we need? Note that we're already > > The arm-smmu driver doesn't, but there's no fundamental reason it > couldn't. That should just need code to refcount domain users and > release hardware contexts for domains with no devices currently attached. > > Robin. > > > doing that, except that we're doing it behind the back of the DMA > > mapping subsystem, so that it keeps using the IOMMU version of the DMA > > ops for the device and doing any mapping operations on the default > > domain. If we ask the DMA mapping to detach, wouldn't it essentially > > solve the problem? Thanks Robin. Still, my point is that the MSM DRM driver attaches the GPU struct device to a new domain it allocates using iommu_domain_alloc() and it seems to work fine, so I believe it's not the problem we're looking into with this patch. Best regards, Tomasz