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Subject: Re: [PATCH v2 1/4] irqchip: sifive-plic: Pre-compute context hart
 base and enable base
To:     Anup Patel <anup@brainfault.org>,
        Palmer Dabbelt <palmer@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>,
        Marc Zyngier <marc.zyngier@arm.com>
Cc:     Christoph Hellwig <hch@infradead.org>,
        "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
References: <20181127100317.12809-1-anup@brainfault.org>
 <20181127100317.12809-2-anup@brainfault.org>
From:   Atish Patra <atish.patra@wdc.com>
Message-ID: <b6ff2593-9113-9b95-ade5-09e7e9fa1be5@wdc.com>
Date:   Thu, 29 Nov 2018 16:35:21 -0800
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On 11/27/18 2:03 AM, Anup Patel wrote:
> This patch does following optimizations:
> 1. Pre-compute hart base for each context handler
> 2. Pre-compute enable base for each context handler
> 3. Have enable lock for each context handler instead
> of global plic_toggle_lock
> 
> Signed-off-by: Anup Patel <anup@brainfault.org>
> ---
>   drivers/irqchip/irq-sifive-plic.c | 41 +++++++++++++------------------
>   1 file changed, 17 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> index 357e9daf94ae..56fce648a901 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -60,36 +60,24 @@ static void __iomem *plic_regs;
>   struct plic_handler {
>   	bool			present;
>   	int			ctxid;
> +	void __iomem		*hart_base;
> +	raw_spinlock_t		enable_lock;
> +	void __iomem		*enable_base;

It should be u32. Otherwise, plic_toggle calculates incorrect address 
and it does not boot on Unlheased.

>   };
>   static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
>   
> -static inline void __iomem *plic_hart_offset(int ctxid)
> +static inline void plic_toggle(struct plic_handler *handler,
> +				int hwirq, int enable)
>   {
> -	return plic_regs + CONTEXT_BASE + ctxid * CONTEXT_PER_HART;
> -}
> -
> -static inline u32 __iomem *plic_enable_base(int ctxid)
> -{
> -	return plic_regs + ENABLE_BASE + ctxid * ENABLE_PER_HART;
> -}
> -
> -/*
> - * Protect mask operations on the registers given that we can't assume that
> - * atomic memory operations work on them.
> - */

Should we keep the comment for enable_lock ?

> -static DEFINE_RAW_SPINLOCK(plic_toggle_lock);
> -
> -static inline void plic_toggle(int ctxid, int hwirq, int enable)
> -{
> -	u32 __iomem *reg = plic_enable_base(ctxid) + (hwirq / 32);
> +	u32 __iomem *reg = handler->enable_base + (hwirq / 32);
>   	u32 hwirq_mask = 1 << (hwirq % 32);
>   
> -	raw_spin_lock(&plic_toggle_lock);
> +	raw_spin_lock(&handler->enable_lock);
>   	if (enable)
>   		writel(readl(reg) | hwirq_mask, reg);
>   	else
>   		writel(readl(reg) & ~hwirq_mask, reg);
> -	raw_spin_unlock(&plic_toggle_lock);
> +	raw_spin_unlock(&handler->enable_lock);
>   }
>   
>   static inline void plic_irq_toggle(struct irq_data *d, int enable)
> @@ -101,7 +89,7 @@ static inline void plic_irq_toggle(struct irq_data *d, int enable)
>   		struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
>   
>   		if (handler->present)
> -			plic_toggle(handler->ctxid, d->hwirq, enable);
> +			plic_toggle(handler, d->hwirq, enable);
>   	}
>   }
>   
> @@ -150,7 +138,7 @@ static struct irq_domain *plic_irqdomain;
>   static void plic_handle_irq(struct pt_regs *regs)
>   {
>   	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
> -	void __iomem *claim = plic_hart_offset(handler->ctxid) + CONTEXT_CLAIM;
> +	void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
>   	irq_hw_number_t hwirq;
>   
>   	WARN_ON_ONCE(!handler->present);
> @@ -240,11 +228,16 @@ static int __init plic_init(struct device_node *node,
>   		handler = per_cpu_ptr(&plic_handlers, cpu);
>   		handler->present = true;
>   		handler->ctxid = i;
> +		handler->hart_base =
> +			plic_regs + CONTEXT_BASE + i * CONTEXT_PER_HART;
> +		raw_spin_lock_init(&handler->enable_lock);
> +		handler->enable_base =
> +			plic_regs + ENABLE_BASE + i * ENABLE_PER_HART;
>   
>   		/* priority must be > threshold to trigger an interrupt */
> -		writel(0, plic_hart_offset(i) + CONTEXT_THRESHOLD);
> +		writel(0, handler->hart_base + CONTEXT_THRESHOLD);
>   		for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
> -			plic_toggle(i, hwirq, 0);
> +			plic_toggle(handler, hwirq, 0);
>   		nr_mapped++;
>   	}
>   
>