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[209.132.180.67]) by mx.google.com with ESMTP id c5si3514330pgq.434.2018.11.29.17.17.34; Thu, 29 Nov 2018 17:17:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=rGUynLRc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727295AbeK3MXI (ORCPT + 99 others); Fri, 30 Nov 2018 07:23:08 -0500 Received: from mail-io1-f65.google.com ([209.85.166.65]:34375 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726393AbeK3MXI (ORCPT ); Fri, 30 Nov 2018 07:23:08 -0500 Received: by mail-io1-f65.google.com with SMTP id f6so3243030iob.1; Thu, 29 Nov 2018 17:15:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=W3FONXkWY3U3pEkDPvnZpRUi0YhWKLbdocI43n/pciM=; b=rGUynLRcICf8A4Y6KXsm64hY5gIIt2LfgqHK6x1QuzdbldWuG/DpDhc0zqG5MVxSgi RMkBWzd6g8JcuZ2umcShVNCXYnr3YR08x2l3IFxNOa2P0T6htDD80LGb6NXY6PAY8y9s 4PGVMwGFFSjTKgP5pEjgKcDMotglcHjSPVOtoz+DiTUwFRTavU6yhjJHom/7oIKLaFiY GSuDIPPn1+5hDdxxCAiNRyTqhs5aF0NxRhvETmGMlzfljAC2Nyk7Cgb4P/8ksctfXGLm b5v3OabjSoWAlyvV8/5Si4NUKnMCWFEmHa2UvLYrwrpSfhOpiMyZAbjdL08zV5pjk/YY lELw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=W3FONXkWY3U3pEkDPvnZpRUi0YhWKLbdocI43n/pciM=; b=D9E/2bQD8j0/jOXMbl9Nu/bDy4Pip6Qgt51AhOZHVHOomhNnLY4jODdDmjKadvkVHf PUbzTHq5fNVCT2s1nsK6Z5GwzLsxWD3QCvGVTV3lLZBOFquhp8paGwM+IpIM0xPZB8Bx R8EOk0dUphVWqSi6nw1nhdl6Nh4GhyWzXSx1PbpM1iXOoo2qgwdIRw0r0F96T4eZJ8zA s4u3ysj6dZI8Y/XcIz7Li9IeZSC1Gp/kLMCAft47O9BSmzIG+qfNlcN3ADFRZ6eyhkLh arxUUcuRajEPno0S7XDx85SIWRrVwxs0xg4Oi0vkTdi2VUImfX7o65o3ofhcQYOJ9+gY flZQ== X-Gm-Message-State: AA+aEWZRvKDupzr4Etc6EGgZ+fDkdQVQL82bKw64o/quzIADgmXMpLQs w0IVjzUi8e35vNSwYIoz8UDiDHb3pR4BTY1c8DU= X-Received: by 2002:a5e:8b46:: with SMTP id z6mr3083934iom.7.1543540538031; Thu, 29 Nov 2018 17:15:38 -0800 (PST) MIME-Version: 1.0 References: <20181129140315.28476-1-vivek.gautam@codeaurora.org> <20181129141429.GA22638@lst.de> <20181129155758.GC26537@lst.de> In-Reply-To: <20181129155758.GC26537@lst.de> From: Rob Clark Date: Thu, 29 Nov 2018 20:15:23 -0500 Message-ID: Subject: Re: [PATCH v3 1/1] drm: msm: Replace dma_map_sg with dma_sync_sg* To: hch@lst.de Cc: Daniel Vetter , David Airlie , linux-arm-msm , Linux Kernel Mailing List , dri-devel , Tomasz Figa , Sean Paul , Vivek Gautam , freedreno , Robin Murphy Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 29, 2018 at 10:57 AM Christoph Hellwig wrote: > > On Thu, Nov 29, 2018 at 03:43:50PM +0100, Daniel Vetter wrote: > > Yeah we had patches to add manual cache management code to drm, so we > > don't have to abuse the dma streaming api anymore. Got shouted down. > > Abusing the dma streaming api also gets shouted down. It's a gpu, any > > idea of these drivers actually being platform independent is out of > > the window from the start anyway, so we're ok with tying this to > > platforms. > > Manual or not the iommu API is missing APIs for cache management, > which makes it kinda surprising it actually ever worked for non-coherent > devices. > > And fortunately while some people spent the last year ot two bickering > about the situation others actually did work, and we now have a > generic arch_sync_dma_for_device/arch_sync_dma_for_cpu kernel-internal > API. This is only used for DMA API internals so far, and explicitly > not intended for direct driver use, but it would be perfect as the > backend for iommu API cache maintainance functions. It exists on all > but two architectures on mainline. Out of those powerpc is in the works, > only arm32 will need some major help. oh, hmm, I realized I'd been looking still at the armv7 dma-mapping, I hadn't noticed arch_sync_* yet.. that does look like a step in the right direction. As far as hiding cache ops behind iommu layer, I guess I'd been thinking more of just letting the drivers that want to bypass dma layer take things into their own hands.. tbh I think/assume/hope drm/msm is more the exception than the rule as far as needing to bypass the dma layer. Or at least I guess the # of drivers having problems w/ the dma layer is less than the # of iommu drivers. (Not sure if that changes my thoughts on this patch, it isn't like what this patch replaces isn't also a problematic hack around the inability to bypass the dma layer. In the short term I just want *something* that works, I'm totally happy to refactor later when there are better options.) BR, -R