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[209.132.180.67]) by mx.google.com with ESMTP id c17si4162246pgl.385.2018.11.29.22.44.34; Thu, 29 Nov 2018 22:44:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=bcGabfnU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726712AbeK3RwO (ORCPT + 99 others); Fri, 30 Nov 2018 12:52:14 -0500 Received: from mail.kernel.org ([198.145.29.99]:44402 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726498AbeK3RwO (ORCPT ); Fri, 30 Nov 2018 12:52:14 -0500 Received: from localhost (unknown [104.132.0.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 624CA20863; Fri, 30 Nov 2018 06:43:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1543560238; bh=1KbS/H6E5H0W1qh4RtVpQWod+3yOS5qydDBCJ/kE3fQ=; h=To:From:In-Reply-To:Cc:References:Subject:Date:From; b=bcGabfnUaY7qhe71t8JtmyGOqInchiNtzvyFGGQ87JC6XIEOm7Ll9N2KALe382057 vfB+KM2zou0sWmD+Wu0NaoZBeueD0J9hL+YEJyKoWPIJWZwk9iPrBfrCWjntSMX00/ 3XY35oXIolDpVSO+IwkIOJS+U2kTMDijrSxd0b88= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: Matthias Brugger , Matthias Brugger , Rob Herring From: Stephen Boyd In-Reply-To: <458178ac-c0fc-9671-7fc8-ed2d6f61424c@suse.com> Cc: matthias.bgg@kernel.org, Mark Rutland , CK Hu , Philipp Zabel , David Airlie , Michael Turquette , Stephen Boyd , Ulrich Hecht , Laurent Pinchart , Sean Wang , Sean Wang , Randy Dunlap , Chen-Yu Tsai , dri-devel , "linux-kernel@vger.kernel.org" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , linux-mediatek@lists.infradead.org, linux-clk , devicetree@vger.kernel.org References: <20181116125449.23581-1-matthias.bgg@kernel.org> <20181116125449.23581-9-matthias.bgg@kernel.org> <20181116231522.GA18006@bogus> <2a23e407-4cd4-2e2b-97a5-4e2bb96846e0@gmail.com> <154281878765.88331.10581984256202566195@swboyd.mtv.corp.google.com> <458178ac-c0fc-9671-7fc8-ed2d6f61424c@suse.com> Message-ID: <154356023767.88331.18401188808548429052@swboyd.mtv.corp.google.com> User-Agent: alot/0.7 Subject: Re: [PATCH v5 08/12] dt-bindings: mediatek: Change the binding for mmsys clocks Date: Thu, 29 Nov 2018 22:43:57 -0800 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Matthias Brugger (2018-11-21 09:09:52) > = > = > On 21/11/2018 17:46, Stephen Boyd wrote: > > Quoting Rob Herring (2018-11-19 11:15:16) > >> On Sun, Nov 18, 2018 at 11:12 AM Matthias Brugger > >> wrote: > >>> On 11/17/18 12:15 AM, Rob Herring wrote: > >>>> On Fri, Nov 16, 2018 at 01:54:45PM +0100, matthias.bgg@kernel.org wr= ote: > >>>>> - #clock-cells =3D <1>; > >>>>> + > >>>>> + mmsys_clk: clock-controller@14000000 { > >>>>> + compatible =3D "mediatek,mt2712-mmsys-clk"; > >>>>> + #clock-cells =3D <1>; > >>>> > >>>> This goes against the general direction of not defining separate nod= es > >>>> for providers with no resources. > >>>> > >>>> Why do you need this and what does it buy if you have to continue to > >>>> support the existing chips? > >>>> > >>> > >>> It would show explicitly that the mmsys block is used to probe two > >>> drivers, one for the gpu and one for the clocks. Otherwise that is > >>> hidden in the drm driver code. I think it is cleaner to describe that= in > >>> the device tree. > >> > >> No, that's maybe cleaner for the driver implementation in the Linux > >> kernel. What about other OS's or when Linux drivers and subsystems > >> needs change? Cleaner for DT is design bindings that reflect the h/w. > >> Hardware is sometimes just messy. > >> > > = > > I agree. I fail to see what this patch series is doing besides changing > > driver probe and device creation methods and making a backwards > > incompatible change to DT. Is there any other benefit here? > > = > = > You are referring whole series? > Citing the cover letter: > "MMSYS in Mediatek SoCs has some registers to control clock gates (which = is > used in the clk driver) and some registers to set the routing and enable > the differnet (sic!) blocks of the display subsystem. > = > Up to now both drivers, clock and drm are probed with the same device tree > compatible. But only the first driver get probed, which in effect breaks > graphics on mt8173 and mt2701. Ouch! > = > This patch uses a platform device registration in the DRM driver, which > will trigger the probe of the corresponding clock driver. It was tested o= n the > bananapi-r2 and the Acer R13 Chromebook." Alright, please don't add nodes in DT just to make device drivers probe. Instead, register clks from the drm driver or create a child platform device for the clk bits purely in the drm driver and have that probe the associated clk driver from there. > = > DT is broken right now, because two drivers rely on the same node, which = gets > consumed just once. The new DT introduced does not break anything because= it is > only used for boards that: "[..] are not available to the general public > (mt2712e) or only have the mmsys clock driver part implemented (mt6797)." Ok, so backwards compatibility is irrelevant then. Sounds fine to me.