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Subject: Re: Resend: How to handle the SMMU RAS Error in the kernel
To:     gengdongjiu <gengdongjiu@huawei.com>,
        gengdongjiu <gengdj.1984@gmail.com>
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        xuqiang36@huawei.com,
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From:   James Morse <james.morse@arm.com>
Message-ID: <c769e2a5-f176-60fd-bcff-ef00e904736a@arm.com>
Date:   Fri, 30 Nov 2018 18:37:29 +0000
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Hi gengdongjiu,

On 21/11/2018 08:10, gengdongjiu wrote:
> On 2018/11/20 2:05, James Morse wrote:
>> On 17/11/2018 15:41, gengdongjiu wrote:
>>> In the current kernel, it only handles three kinds of error, which is
>>> memory error, PCIE device and ARM process. But now the SMMU already
>>> support the RAS, how to handle the SMMU RAS error in the kernel?
>>
>> What errors are being detected here?
>>
>> I don't know much about the SMMU, but I think we should start with a list of
>> errors that we want to handle.
> 
> In our platform, the SMMU RAS error mainly include below which flow the SMMU spec:
> 1. one bit ECC error, reported as CE.
> 2. two bits ECC error, reported as UEU.
> 3. fetch error in the SMMUv3 spec, reported as UER.

These are faults, but this isn't enough information for software to act on.

Are these faults in the device, host-memory, or memory that is part of the SMMU?
Was the error discovered during a read/write by the device?, (which one?) Or the
SMMU's page-tables, or command-queue.


> The 2 and 3 should be handled, but I do not know how do recovery to it.

Me neither. If we can come up with the errors that can be detected, we can work
out which ones can be handled.


Thanks,

James