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From:   Vineet Gupta <vineet.gupta1@synopsys.com>
To:     David Laight <David.Laight@ACULAB.COM>,
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        Joao Pinto <joao.pinto@synopsys.com>,
        Vitor Soares <vitor.soares@synopsys.com>
Subject: Re: [PATCH v2] ARC: io.h: Implement reads{x}()/writes{x}()
Thread-Topic: [PATCH v2] ARC: io.h: Implement reads{x}()/writes{x}()
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Date:   Fri, 30 Nov 2018 19:00:05 +0000
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On 11/30/18 5:57 AM, David Laight wrote:=0A=
> There're even identical opcodes...=0A=
> The barrier() (etc) in the asm output probably stopped the optimisation.=
=0A=
>=0A=
> It also seems to have used a different type of loop to the=0A=
> other example, probably less efficient.=0A=
> (Not that I'm an expert on ARC opcodes.)=0A=
=0A=
The difference is due to ISA and ensuing ARC gcc backends. ARCompact based =
cores=0A=
don't support unaligned access and the loop there was ZOL (Zero delay loop)=
. In=0A=
ARCv2 based cores, the gcc backend has been tweaked to generate fewer ZOLs =
hence=0A=
you see the more canonical tst and branch style loop.=0A=
=0A=
-Vineet=0A=