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Sat, 1 Dec 2018 03:13:35 -0800 Received: from [172.23.64.8] (helo=xhdvnc108.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1gT3DL-0001k5-3f; Sat, 01 Dec 2018 03:13:35 -0800 Received: by xhdvnc108.xilinx.com (Postfix, from userid 15427) id 5089160503; Sat, 1 Dec 2018 16:43:34 +0530 (IST) From: Anurag Kumar Vulisha To: Felipe Balbi , Greg Kroah-Hartman , Shuah Khan , Alan Stern , Johan Hovold , Jaejoong Kim , Benjamin Herrenschmidt , Roger Quadros , Manu Gautam , , Bart Van Assche , Mike Christie , Matthew Wilcox , Colin Ian King CC: , , , Thinh Nguyen , Tejas Joglekar , Ajay Yugalkishore Pandey , Anurag Kumar Vulisha Subject: [PATCH v7 09/10] usb: dwc3: Check for IOC/LST bit in both event->status and TRB->ctrl fields Date: Sat, 1 Dec 2018 16:43:30 +0530 Message-ID: <1543662811-5194-10-git-send-email-anurag.kumar.vulisha@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1543662811-5194-1-git-send-email-anurag.kumar.vulisha@xilinx.com> References: <1543662811-5194-1-git-send-email-anurag.kumar.vulisha@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(376002)(39860400002)(136003)(346002)(396003)(2980300002)(199004)(189003)(8936002)(76176011)(51416003)(446003)(426003)(48376002)(336012)(106002)(356004)(6666004)(47776003)(16586007)(316002)(110136005)(54906003)(42186006)(36386004)(50466002)(14444005)(8676002)(486006)(2906002)(103686004)(39060400002)(36756003)(4326008)(106466001)(5660300001)(186003)(81166006)(81156014)(26005)(90966002)(478600001)(52956003)(50226002)(11346002)(63266004)(476003)(126002)(2616005)(7416002)(107886003)(6266002)(2171002)(305945005)(107986001)(921003)(1121003)(83996005)(2101003);DIR:OUT;SFP:1101;SCL:1;SRVR:CY4PR0201MB3508;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;A:1;MX:1; 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This logic doesn't work if multiple TRBs are queued per request and the IOC/LST bit is set on the last TRB of that request. Consider an example where a queued request has multiple queued TRBs and IOC/LST bit is set only for the last TRB. In this case, the Core generates XferComplete/XferInProgress events only for the last TRB (since IOC/LST are set only for the last TRB). As per the logic in dwc3_gadget_ep_reclaim_completed_trb() event->status is checked for IOC/LST bit and returns on the first TRB. This makes the remaining TRBs left unhandled. To aviod this, changed the code to check for IOC/LST bits in both event->status & TRB->ctrl. This patch does the same. Signed-off-by: Anurag Kumar Vulisha Reviewed-by: Thinh Nguyen Tested-by: Tejas Joglekar --- Changes in v7: 1. None Changes in v6: 1. None Changes in v5: 1. None Changes in v4: 1. None Changes in v3: 1. None Changes in v2: 1. None --- drivers/usb/dwc3/gadget.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 9ddc9fd..216179e 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -2286,7 +2286,12 @@ static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep, if (event->status & DEPEVT_STATUS_SHORT && !chain) return 1; - if (event->status & (DEPEVT_STATUS_IOC | DEPEVT_STATUS_LST)) + if ((event->status & DEPEVT_STATUS_IOC) && + (trb->ctrl & DWC3_TRB_CTRL_IOC)) + return 1; + + if ((event->status & DEPEVT_STATUS_LST) && + (trb->ctrl & DWC3_TRB_CTRL_LST)) return 1; return 0; -- 2.1.1