Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp5889628imu; Sun, 2 Dec 2018 05:48:11 -0800 (PST) X-Google-Smtp-Source: AFSGD/V9YtxUUAsDOd/8bn56bqALhmlltVSChGdzocPJCBHnm16M9gMi771urftrgMUBj4FipHBa X-Received: by 2002:a17:902:7d90:: with SMTP id a16mr3432729plm.249.1543758491211; Sun, 02 Dec 2018 05:48:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543758491; cv=none; d=google.com; s=arc-20160816; b=e8vgDH6en5rf4QEbjZPAyic9g19YaG7u9x95NkS/TVl7HfW0oo6O+nBEtF2P9PEPnG LEw9tUEZ30dPqyUv6JyOz9jeyxJA1AuqbMXjigSOTZMuhak2LAoJgqxnyGrt8BJEYtq/ 252Sn+4l+qWyX2o7kN/HVJOtFpsq2QY6xfk4322zLi5GMtsB6iKeKfS8v/POxnEHk2nf QbF081zlkNJsPHAxIov2hyJ+XFjAT9UznangroTpVLJBku562dV9gqbbyin39qVrBtkZ emZdUjhEDexfv5p/Rr9qYr8vv2Z9rDF4tiSU19by4SC0Q/ZzZFO/eMvzlK5yH9jp8VU8 79Xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :organization:references:in-reply-to:date:cc:to:from:subject :message-id; bh=9xa8QsZygCUmCSrmpOQzWxudyEEfTTv6gUnyAebsCAA=; b=MucwrcLyw3tvnTZ0EBhsUJUCqYau6v96GXIQJZU8bsMwQOyzcRmnr8mkxvFIV5cSKU 3zh3qM36d7I//shw/Km57Eh7H0hhoD6VP4Qp0TytwNYoiLoejjuzmCrS9OiDfABO5wj7 MvRgbRR/J5HZ2iJ831syJx3gKY/RWX7oxMV2fX+nLvQYM8GIqlaR7uj0RtRTSc6p6lYo XcgDIRxQNArJi/3f7bKNWxk7WKMcSCYvOrMu0OTR+eGDGeXINu02t6NzJUQ5Dh0PfJoz S7ITU5exK6i/gWJYFM1Zs7IpFMmCct5+Od5yQEpsG0m6uD1m3kWVrATCPNZF9OEJ+9h2 UQOA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l24si10079368pgb.489.2018.12.02.05.47.56; Sun, 02 Dec 2018 05:48:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725890AbeLBNqu (ORCPT + 99 others); Sun, 2 Dec 2018 08:46:50 -0500 Received: from hermes.aosc.io ([199.195.250.187]:55630 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725843AbeLBNqu (ORCPT ); Sun, 2 Dec 2018 08:46:50 -0500 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 4F0D911ED4A; Sun, 2 Dec 2018 13:46:42 +0000 (UTC) Message-ID: <41099855eb644a004ebf67059232a53146b278c1.camel@aosc.io> Subject: Re: [PATCH 1/2] dt-bindings: gpu: add bus clock for Mali Midgard GPUs From: Icenowy Zheng To: Jernej Skrabec , Chen-Yu Tsai , Maxime Ripard , David Airlie , Rob Herring , Mark Rutland Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Date: Sun, 02 Dec 2018 21:46:37 +0800 In-Reply-To: <20181127074249.15204-1-icenowy@aosc.io> References: <20181127074249.15204-1-icenowy@aosc.io> Organization: Anthon Open-Source Community Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 在 2018-11-27二的 15:42 +0800,Icenowy Zheng写道: > Some SoCs adds a bus clock gate to the Mali Midgard GPU. > > Add the binding for the bus clock. > > Signed-off-by: Icenowy Zheng Could anyone have a check on this patchset? > --- > Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 > ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali- > midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali- > midgard.txt > index 18a2cde2e5f3..02f870cd60e6 100644 > --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt > @@ -31,6 +31,12 @@ Optional properties: > > - clocks : Phandle to clock for the Mali Midgard device. > > +- clock-names : Specify the names of the clocks specified in clocks > + when multiple clocks are present. > + * bus: bus clock for the GPU > + * core: clock driving the GPU itself (When only one clock is > present, > + assume it's this clock.) > + > - mali-supply : Phandle to regulator for the Mali device. Refer to > Documentation/devicetree/bindings/regulator/regulator.txt for > details. >