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From:   <jiada_wang@mentor.com>
To:     <broonie@kernel.org>, <perex@perex.cz>, <tiwai@suse.com>,
        <kuninori.morimoto.gx@renesas.com>, <vladimir_zapolskiy@mentor.com>
CC:     <alsa-devel@alsa-project.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH linux-next v2 0/6] clk: renesas: adg: add AVB Clock
Date:   Mon, 3 Dec 2018 20:21:54 +0900
Message-ID: <20181203112200.18220-1-jiada_wang@mentor.com>
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From: Jiada Wang <jiada_wang@mentor.com>

on R-Car SoCs there are AVB Counter Clocks, each clock has 12bits integral
and 8 bits fractional dividers which operates with S0D1ϕ clock.

This patch-set adds 'adg' clock to R-Car Soc, and changes adg driver to
register avb clocks when clock-cells of rcar_sound node is 2.

---
v2:
- expends adg register size and register avb clocks instead of
  add new clk-avb driver
- Add adg clock 

v1: initial version

Jiada Wang (2):
  dt-bindings: clock: add clock id for renesas adg clocks
  ASoC: rsnd: add avb clocks

Takeshi Kihara (4):
  clk: renesas: r8a7795: Add ADG clock
  clk: renesas: r8a7796: Add ADG clock
  clk: renesas: r8a77990: Add ADG clocks
  clk: renesas: r8a77995: Add ADG clock

 drivers/clk/renesas/r8a7795-cpg-mssr.c  |   1 +
 drivers/clk/renesas/r8a7796-cpg-mssr.c  |   1 +
 drivers/clk/renesas/r8a77990-cpg-mssr.c |   1 +
 drivers/clk/renesas/r8a77995-cpg-mssr.c |   1 +
 include/dt-bindings/clock/renesas-adg.h |  11 +
 sound/soc/sh/rcar/adg.c                 | 306 +++++++++++++++++++++++-
 sound/soc/sh/rcar/gen.c                 |   9 +
 sound/soc/sh/rcar/rsnd.h                |   9 +
 8 files changed, 330 insertions(+), 9 deletions(-)
 create mode 100644 include/dt-bindings/clock/renesas-adg.h

-- 
2.17.0