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From:   Ayan Halder <Ayan.Halder@arm.com>
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CC:     nd <nd@arm.com>
Subject: [RFC AFBC 11/12] drm/arm/malidp:- Disregard the pitch alignment
 constraint for AFBC framebuffer.
Thread-Topic: [RFC AFBC 11/12] drm/arm/malidp:- Disregard the pitch alignment
 constraint for AFBC framebuffer.
Thread-Index: AQHUivvRde0QVAJcak6cnHk/9XEoiw==
Date:   Mon, 3 Dec 2018 11:32:05 +0000
Message-ID: <1543836703-8491-12-git-send-email-ayan.halder@arm.com>
References: <1543836703-8491-1-git-send-email-ayan.halder@arm.com>
In-Reply-To: <1543836703-8491-1-git-send-email-ayan.halder@arm.com>
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Considering the fact that some of the AFBC specific pixel formats are expre=
ssed
in bits per pixel (ie bpp which is not byte aligned), the pitch (ie width *=
 bpp)
is not guaranteed to be aligned to burst size (ie 8 or 16 bytes).
For example, DRM_FORMAT_VUY101010 is 30 bits per pixel. For a framebuffer o=
f
width 32 pixels, the pitch will be 120 bytes which is not aligned to burst =
size
(ie 16 bytes) for DP650.

Signed-off-by: Ayan Kumar halder <ayan.halder@arm.com>
---
 drivers/gpu/drm/arm/malidp_planes.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/mali=
dp_planes.c
index d0a00ee..eec0442 100644
--- a/drivers/gpu/drm/arm/malidp_planes.c
+++ b/drivers/gpu/drm/arm/malidp_planes.c
@@ -529,8 +529,8 @@ static int malidp_de_plane_check(struct drm_plane *plan=
e,
 	for (i =3D 0; i < ms->n_planes; i++) {
 		u8 alignment =3D malidp_hw_get_pitch_align(mp->hwdev, rotated);
=20
-		if ((fb->pitches[i] * drm_format_info_block_height(fb->format, i))
-				& (alignment - 1)) {
+		if (((fb->pitches[i] * drm_format_info_block_height(fb->format, i))
+				& (alignment - 1)) && !(fb->modifier)) {
 			DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n",
 				      fb->pitches[i], i);
 			return -EINVAL;
--=20
2.7.4