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From:   Ayan Halder <Ayan.Halder@arm.com>
To:     Ayan Halder <Ayan.Halder@arm.com>,
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CC:     nd <nd@arm.com>
Subject: [RFC AFBC 05/12] drm/arm/malidp:- Define a common list of AFBC format
 modifiers supported for DP500, DP550 and DP650
Thread-Topic: [RFC AFBC 05/12] drm/arm/malidp:- Define a common list of AFBC
 format modifiers supported for DP500, DP550 and DP650
Thread-Index: AQHUivvNKeBDbJPJl0CSbSfIg6+TSg==
Date:   Mon, 3 Dec 2018 11:31:59 +0000
Message-ID: <1543836703-8491-6-git-send-email-ayan.halder@arm.com>
References: <1543836703-8491-1-git-send-email-ayan.halder@arm.com>
In-Reply-To: <1543836703-8491-1-git-send-email-ayan.halder@arm.com>
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We need to define a common list of format modifiers supported by each of th=
e Mali
display processors. The difference between DP500 from DP550/650 is that DP5=
00
does not support block split mode (ie AFBC_FORMAT_MOD_SPLIT) and DP550 supp=
orts
YUV420 with split mode. We noted these special cases by defining MALIDP_DEV=
ICE_AFBC_SUPPORT_SPLIT
and AFBC_SUPPORT_SPLIT_WITH_YUV_420_10 for malidp_hw_regmap.features

Also we have defined a set of meaningful macros to shorten the modifier nam=
es

Signed-off-by: Ayan Kumar halder <ayan.halder@arm.com>

Change-Id: I09fba2032a7474e6ce45af230e0ed18fc1f4c1df
---
 drivers/gpu/drm/arm/malidp_drv.c |  8 ++++----
 drivers/gpu/drm/arm/malidp_hw.c  | 30 ++++++++++++++++++++++++++++--
 drivers/gpu/drm/arm/malidp_hw.h  | 20 +++++++++++++++-----
 3 files changed, 47 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_=
drv.c
index 505f316..b8db92f 100644
--- a/drivers/gpu/drm/arm/malidp_drv.c
+++ b/drivers/gpu/drm/arm/malidp_drv.c
@@ -293,8 +293,8 @@ malidp_verify_afbc_framebuffer_caps(struct drm_device *=
dev,
 		return false;
 	}
=20
-	switch (mode_cmd->modifier[0] & AFBC_FORMAT_MOD_BLOCK_SIZE_MASK) {
-	case AFBC_FORMAT_MOD_BLOCK_SIZE_16x16:
+	switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) {
+	case AFBC_SIZE_16X16:
 		if ((mode_cmd->width % 16) || (mode_cmd->height % 16)) {
 			DRM_DEBUG_KMS("AFBC buffers must be aligned to 16 pixels\n");
 			return false;
@@ -319,8 +319,8 @@ malidp_verify_afbc_framebuffer_size(struct drm_device *=
dev,
 	u32 afbc_superblock_size =3D 0, afbc_superblock_height =3D 0;
 	u32 afbc_superblock_width =3D 0, afbc_size =3D 0;
=20
-	switch (mode_cmd->modifier[0] & AFBC_FORMAT_MOD_BLOCK_SIZE_MASK) {
-	case AFBC_FORMAT_MOD_BLOCK_SIZE_16x16:
+	switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) {
+	case AFBC_SIZE_16X16:
 		afbc_superblock_height =3D 16;
 		afbc_superblock_width =3D 16;
 		break;
diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_h=
w.c
index 87b7b12..55d379b 100644
--- a/drivers/gpu/drm/arm/malidp_hw.c
+++ b/drivers/gpu/drm/arm/malidp_hw.c
@@ -137,6 +137,32 @@ static const struct malidp_layer malidp650_layers[] =
=3D {
 		ROTATE_NONE, 0 },
 };
=20
+const u64 malidp_format_modifiers[] =3D {
+	/* All RGB formats (except XRGB, RGBX, XBGR, BGRX) */
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_YTR | AFBC_SPARSE),
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_YTR),
+
+	/* All RGB formats > 16bpp (except XRGB, RGBX, XBGR, BGRX) */
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_YTR | AFBC_SPARSE | AFBC_S=
PLIT),
+
+	/* All 8 or 10 bit YUV 444 formats. */
+	/* In DP550, 10 bit YUV 420 format also supported */
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_SPARSE | AFBC_SPLIT),
+
+	/* YUV 420, 422 P1 8 bit and YUV 444 8 bit/10 bit formats */
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_SPARSE),
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16),
+
+	/* YUV 420, 422 P1 8, 10 bit formats */
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_CBR | AFBC_SPARSE),
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_SIZE_16X16 | AFBC_CBR),
+
+	/* All formats */
+	DRM_FORMAT_MOD_LINEAR,
+
+	DRM_FORMAT_MOD_INVALID
+};
+
 #define SE_N_SCALING_COEFFS	96
 static const u16 dp500_se_scaling_coeffs[][SE_N_SCALING_COEFFS] =3D {
 	[MALIDP_UPSCALING_COEFFS - 1] =3D {
@@ -841,7 +867,7 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES=
] =3D {
 			.se_base =3D MALIDP550_SE_BASE,
 			.dc_base =3D MALIDP550_DC_BASE,
 			.out_depth_base =3D MALIDP550_DE_OUTPUT_DEPTH,
-			.features =3D MALIDP_REGMAP_HAS_CLEARIRQ,
+			.features =3D MALIDP_REGMAP_HAS_CLEARIRQ | MALIDP_DEVICE_AFBC_SUPPORT_S=
PLIT | AFBC_SUPPORT_SPLIT_WITH_YUV_420_10,
 			.n_layers =3D ARRAY_SIZE(malidp550_layers),
 			.layers =3D malidp550_layers,
 			.de_irq_map =3D {
@@ -887,7 +913,7 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES=
] =3D {
 			.se_base =3D MALIDP550_SE_BASE,
 			.dc_base =3D MALIDP550_DC_BASE,
 			.out_depth_base =3D MALIDP550_DE_OUTPUT_DEPTH,
-			.features =3D MALIDP_REGMAP_HAS_CLEARIRQ,
+			.features =3D MALIDP_REGMAP_HAS_CLEARIRQ | MALIDP_DEVICE_AFBC_SUPPORT_S=
PLIT,
 			.n_layers =3D ARRAY_SIZE(malidp650_layers),
 			.layers =3D malidp650_layers,
 			.de_irq_map =3D {
diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_h=
w.h
index 651558f..27b907f 100644
--- a/drivers/gpu/drm/arm/malidp_hw.h
+++ b/drivers/gpu/drm/arm/malidp_hw.h
@@ -95,7 +95,9 @@ struct malidp_se_config {
 };
=20
 /* regmap features */
-#define MALIDP_REGMAP_HAS_CLEARIRQ	(1 << 0)
+#define MALIDP_REGMAP_HAS_CLEARIRQ				BIT(0)
+#define MALIDP_DEVICE_AFBC_SUPPORT_SPLIT			BIT(1)
+#define AFBC_SUPPORT_SPLIT_WITH_YUV_420_10			BIT(2)
=20
 struct malidp_hw_regmap {
 	/* address offset of the DE register bank */
@@ -390,9 +392,17 @@ static inline void malidp_se_set_enh_coeffs(struct mal=
idp_hw_device *hwdev)
=20
 #define MALIDP_GAMMA_LUT_SIZE		4096
=20
-#define AFBC_MOD_VALID_BITS (AFBC_FORMAT_MOD_BLOCK_SIZE_MASK | \
-			AFBC_FORMAT_MOD_YTR | AFBC_FORMAT_MOD_SPLIT | \
-			AFBC_FORMAT_MOD_SPARSE | AFBC_FORMAT_MOD_CBR | \
-			AFBC_FORMAT_MOD_TILED | AFBC_FORMAT_MOD_SC)
+#define AFBC_SIZE_MASK		AFBC_FORMAT_MOD_BLOCK_SIZE_MASK
+#define AFBC_SIZE_16X16		AFBC_FORMAT_MOD_BLOCK_SIZE_16x16
+#define AFBC_YTR		AFBC_FORMAT_MOD_YTR
+#define AFBC_SPARSE		AFBC_FORMAT_MOD_SPARSE
+#define AFBC_CBR		AFBC_FORMAT_MOD_CBR
+#define AFBC_SPLIT		AFBC_FORMAT_MOD_SPLIT
+#define AFBC_TILED		AFBC_FORMAT_MOD_TILED
+#define AFBC_SC			AFBC_FORMAT_MOD_SC
+
+#define AFBC_MOD_VALID_BITS (AFBC_SIZE_MASK | AFBC_YTR | AFBC_SPLIT | AFBC=
_SPARSE | AFBC_CBR | AFBC_TILED | AFBC_SC)
+
+extern const u64 malidp_format_modifiers[];
=20
 #endif  /* __MALIDP_HW_H__ */
--=20
2.7.4