Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp6832360imu; Mon, 3 Dec 2018 03:38:40 -0800 (PST) X-Google-Smtp-Source: AFSGD/V+gChsKaUNOLkuv8UdDgawhLuzyU+oGIklt7DqboV1BIMoqs9a69ImIMv4RjzGXgb9xCgg X-Received: by 2002:a17:902:5ac7:: with SMTP id g7mr15810518plm.212.1543837120069; Mon, 03 Dec 2018 03:38:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543837120; cv=none; d=google.com; s=arc-20160816; b=bA3A+m4XCeqaM7xTfIeEbBvnzi1g21Xm2KPxj3H7JI9Yi9JtH0UdupqAnla5ZP0IXr o8qogzzHurdlGiJED3L8+wlvFORcKg8TmbLh5u3VQsYmsG91U1rOKAg38O2CNkJ4kEjq 5ZuvQYZpfJFcEeEaM2tQAm3+ev+PMYJJU8rGbUHBkZYq5W7XzWj1qhRmGhaYETCAXkI2 CdAY2oxFsC6/RgOtPqyEDcPALMG5hrGeAlkT3/mGnL/EIsyAbgrYcQBRMxvC3o4OX41d H1z8hfuacOlgQfv4gy4uInZ7YkHmuZz5DWxNYvuUqP5UwvTOTTKvWGfOlZhDGLOu23KS 1WnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=2976BJqidxO3iFrUTkEkzCX601V4BbTW8LViilWNVjA=; b=dmfYJE8YRw+gWxuO0/jEIb5G2vmgoO7Qg8qrPYxGAe+iDhJztixnfBjz75tEE+FJap oJTmkioK2UjcjjlNRp+gb16K9HzQaz9lYsLi19zsCfpuVrFQ4PFWyjch09Tay/X34RsK zsQqJj9Y7dlNW/3Gkqnb6khATzk6UPh2wM4J7okc5xlcp6v/v3dmsgT2g5D9wu+3oUvS ifvYG70Ku7L4VKQN68V/EGqlrwAMt4k2ebB+/alzsuC3zMv+LVXVEVeGV71Pf7MYPmAQ RnBZ3Pieabq7K5Is+IRW5BOwDCwMPcXv5N8xJiip7mCzke8DCV4Pa04eNnNBlQBawLrc cGFg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o22si11131032pgb.584.2018.12.03.03.38.24; Mon, 03 Dec 2018 03:38:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726456AbeLCLhP (ORCPT + 99 others); Mon, 3 Dec 2018 06:37:15 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:14915 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726359AbeLCLhP (ORCPT ); Mon, 3 Dec 2018 06:37:15 -0500 X-UUID: 5597227dba774bf7b7ee081506a8b3e2-20181203 X-UUID: 5597227dba774bf7b7ee081506a8b3e2-20181203 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 287662571; Mon, 03 Dec 2018 19:36:29 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 3 Dec 2018 19:36:28 +0800 Received: from mtkslt301.mediatek.inc (10.21.14.114) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 3 Dec 2018 19:36:28 +0800 From: YT Shen To: Matthias Brugger CC: Rob Herring , Mark Rutland , , , , , , YT Shen Subject: [PATCH 5/8] arm64: dts: add pwm nodes for MT2712 Date: Mon, 3 Dec 2018 19:35:59 +0800 Message-ID: <1543836962-18293-6-git-send-email-yt.shen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1543836962-18293-1-git-send-email-yt.shen@mediatek.com> References: <1543836962-18293-1-git-send-email-yt.shen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Signed-off-by: YT Shen --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 4843376..e9856fe 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -418,6 +418,34 @@ status = "disabled"; }; + pwm: pwm@11006000 { + compatible = "mediatek,mt2712-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM>, + <&pericfg CLK_PERI_PWM0>, + <&pericfg CLK_PERI_PWM1>, + <&pericfg CLK_PERI_PWM2>, + <&pericfg CLK_PERI_PWM3>, + <&pericfg CLK_PERI_PWM4>, + <&pericfg CLK_PERI_PWM5>, + <&pericfg CLK_PERI_PWM6>, + <&pericfg CLK_PERI_PWM7>; + clock-names = "top", + "main", + "pwm1", + "pwm2", + "pwm3", + "pwm4", + "pwm5", + "pwm6", + "pwm7", + "pwm8"; + status = "disabled"; + }; + i2c0: i2c@11007000 { compatible = "mediatek,mt2712-i2c"; reg = <0 0x11007000 0 0x90>, -- 1.9.1