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[209.132.180.67]) by mx.google.com with ESMTP id n184si11432376pgn.95.2018.12.03.04.26.20; Mon, 03 Dec 2018 04:26:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726462AbeLCM0Z (ORCPT + 99 others); Mon, 3 Dec 2018 07:26:25 -0500 Received: from gloria.sntech.de ([185.11.138.130]:47258 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726223AbeLCM0Z (ORCPT ); Mon, 3 Dec 2018 07:26:25 -0500 Received: from we0660.dip.tu-dresden.de ([141.76.178.148] helo=phil.localnet) by gloria.sntech.de with esmtpsa (TLS1.0:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.89) (envelope-from ) id 1gTnHu-0002aR-08; Mon, 03 Dec 2018 13:25:22 +0100 From: Heiko Stuebner To: dri-devel@lists.freedesktop.org Cc: Icenowy Zheng , Jernej Skrabec , Chen-Yu Tsai , Maxime Ripard , David Airlie , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] dt-bindings: gpu: add Allwinner H6 Mali Midgard binding Date: Mon, 03 Dec 2018 13:25:21 +0100 Message-ID: <11894938.HOUtrQJeEF@phil> In-Reply-To: <20181127074249.15204-2-icenowy@aosc.io> References: <20181127074249.15204-1-icenowy@aosc.io> <20181127074249.15204-2-icenowy@aosc.io> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Dienstag, 27. November 2018, 08:42:49 CET schrieb Icenowy Zheng: > Allwinner H6 SoC uses a Mali T720 GPU, which is one of the GPUs in the > Midgard GPU product line. > > Add binding for the H6 Mali Midgard GPU. > > Signed-off-by: Icenowy Zheng > --- > .../devicetree/bindings/gpu/arm,mali-midgard.txt | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt > index 02f870cd60e6..c897dd7be48f 100644 > --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt > @@ -18,6 +18,7 @@ Required properties: > + "amlogic,meson-gxm-mali" > + "rockchip,rk3288-mali" > + "rockchip,rk3399-mali" > + + "allwinner,sun50i-h6-mali" I'd think you might want to keep an alphabetical sorting here, aka above amlogic, otherwise the list will probably become hard to read at some later point. > - reg : Physical base address of the device and length of the register area. > > @@ -44,6 +45,18 @@ Optional properties: > for details. > > > +Vendor-specific bindings > +------------------------ > + > +The Mali GPU is integrated very differently from one SoC to > +another. In order to accomodate those differences, you have the option > +to specify one more vendor-specific compatible, among: > + > + - allwinner,sun50i-h6-mali > + Required properties: > + * resets: phandle to the reset line for the GPU While this paragraph is similar to how it is done in Utgard, I'm wondering why we cannot just describe the "resets" as regular optional property above that. Heiko