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Dong" , "linux-clk@vger.kernel.org" From: Stephen Boyd In-Reply-To: <1542200198-3017-10-git-send-email-aisheng.dong@nxp.com> Cc: "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "mturquette@baylibre.com" , "shawnguo@kernel.org" , Anson Huang , Jacky Bai , dl-linux-imx , "A.s. Dong" , Stephen Boyd References: <1542200198-3017-1-git-send-email-aisheng.dong@nxp.com> <1542200198-3017-10-git-send-email-aisheng.dong@nxp.com> Message-ID: <154386555833.88331.17771094561482296098@swboyd.mtv.corp.google.com> User-Agent: alot/0.7 Subject: Re: [PATCH V6 9/9] clk: imx: add imx7ulp clk driver Date: Mon, 03 Dec 2018 11:32:38 -0800 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting A.s. Dong (2018-11-14 05:02:08) > i.MX7ULP Clock functions are under joint control of the System > Clock Generation (SCG) modules, Peripheral Clock Control (PCC) > modules, and Core Mode Controller (CMC)1 blocks > = > The clocking scheme provides clear separation between M4 domain > and A7 domain. Except for a few clock sources shared between two > domains, such as the System Oscillator clock, the Slow IRC (SIRC), > and and the Fast IRC clock (FIRCLK), clock sources and clock > management are separated and contained within each domain. > = > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > = > This driver only adds clock support in A7 domain. > = > Note that most clocks required to be operated when gated, e.g. pll, > pfd, pcc. And more special cases that scs/ddr/nic mux selecting > different clock source requires that clock to be enabled first, > then we need set CLK_OPS_PARENT_ENABLE flag for them properly. > = > Cc: Stephen Boyd > Cc: Michael Turquette > Cc: Shawn Guo > Cc: Anson Huang > Cc: Bai Ping > Signed-off-by: Dong Aisheng > = > --- Applied to clk-next