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[209.132.180.67]) by mx.google.com with ESMTP id p5si13172343pga.352.2018.12.03.12.58.18; Mon, 03 Dec 2018 12:58:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=CjuBsuRc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=wdc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726034AbeLCU5m (ORCPT + 99 others); Mon, 3 Dec 2018 15:57:42 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:19087 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725952AbeLCU5k (ORCPT ); Mon, 3 Dec 2018 15:57:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1543870660; x=1575406660; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=3mJpoam2A2xj4ZksT23VyuZFVe6fICI7QinZh5RdjX0=; b=CjuBsuRc/lJa1aUXaU8tmSUFSDmp88vQxPVjdYQHosV/yI8lNWYnfh5J F7G37rlYN6wZQeGQegDr3q8Na69hWK/dkw+IQC+vWQbRgFzrFE3YDwz+l ERREk4QeXM2KAa8i+ieN20jrC4kjO8gJhaNx/rdjWITKFPzeYfrYbH2ZF oKTq+SxgAontDTEGlo0wgm1jIJlqykbdM2T3HPwdqT4PjZfomcdkUlzQG FlVLfq9c8y6NBfOpqrDpEIhOqZfYYR2z32Rx0ClNlS3OLQBQxTfh5wL4y Xv5KaU4eRFKHoNAuzJ9P1spumE935fVHqXzvrvuFh7T1uNSDldOJlNUB8 A==; X-IronPort-AV: E=Sophos;i="5.56,311,1539619200"; d="scan'208";a="100519857" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 04 Dec 2018 04:57:39 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP; 03 Dec 2018 12:39:55 -0800 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 03 Dec 2018 12:57:39 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Palmer Dabbelt , Christoph Hellwig , Albert Ou , Atish Patra , Daniel Lezcano , devicetree@vger.kernel.org, Dmitriy Cherkasov , linux-riscv@lists.infradead.org, Mark Rutland , Rob Herring , Thomas Gleixner , Anup Patel , Damien Le Moal Subject: [PATCH 1/4] dt-bindings: Correct RISC-V's timebase-frequency Date: Mon, 3 Dec 2018 12:57:28 -0800 Message-Id: <1543870651-16669-2-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1543870651-16669-1-git-send-email-atish.patra@wdc.com> References: <1543870651-16669-1-git-send-email-atish.patra@wdc.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Palmer Dabbelt Someone must have read the device tree specification incorrectly, because we were putting timebase-frequency in the wrong place. This corrects the issue, moving it from / { cpus { timebase-frequency = X; } } to / { cpus { cpu@0 { timebase-frequency = X; } } } This is great, because the timer's frequency should really be a per-cpu quantity on RISC-V systems since there's a timer per CPU. This should lead to some cleanups in our timer driver. Signed-off-by: Palmer Dabbelt Signed-off-by: Christoph Hellwig Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt index adf7b7af..b0b038d6 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.txt +++ b/Documentation/devicetree/bindings/riscv/cpus.txt @@ -93,9 +93,9 @@ Linux is allowed to run on. cpus { #address-cells = <1>; #size-cells = <0>; - timebase-frequency = <1000000>; cpu@0 { clock-frequency = <1600000000>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>; @@ -113,6 +113,7 @@ Linux is allowed to run on. }; cpu@1 { clock-frequency = <1600000000>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -145,6 +146,7 @@ Example: Spike ISA Simulator with 1 Hart This device tree matches the Spike ISA golden model as run with `spike -p1`. cpus { + timebase-frequency = <1000000>; cpu@0 { device_type = "cpu"; reg = <0x00000000>; -- 2.7.4