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From:   Naga Sureshkumar Relli <nagasure@xilinx.com>
To:     Boris Brezillon <boris.brezillon@bootlin.com>
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Subject: RE: [LINUX PATCH v12 3/3] mtd: rawnand: arasan: Add support for
 Arasan NAND Flash Controller
Thread-Topic: [LINUX PATCH v12 3/3] mtd: rawnand: arasan: Add support for
 Arasan NAND Flash Controller
Thread-Index: AQHUd+lSRlJXewM/lk6msOyQbhKEh6VY60OAgBWAFRA=
Date:   Tue, 4 Dec 2018 09:18:53 +0000
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Hi Boris,

> -----Original Message-----
> From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> Sent: Tuesday, November 20, 2018 9:55 PM
> To: Naga Sureshkumar Relli <nagasure@xilinx.com>
> Cc: miquel.raynal@bootlin.com; richard@nod.at; dwmw2@infradead.org;
> computersforpeace@gmail.com; marek.vasut@gmail.com; Michal Simek
> <michals@xilinx.com>; nagasuresh12@gmail.com; linux-mtd@lists.infradead.o=
rg; linux-
> kernel@vger.kernel.org; robh@kernel.org
> Subject: Re: [LINUX PATCH v12 3/3] mtd: rawnand: arasan: Add support for =
Arasan
> NAND Flash Controller
>=20
> On Fri, 9 Nov 2018 10:30:41 +0530
> Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> wrote:
>=20
> > +static int anfc_setup_data_interface(struct nand_chip *chip, int cslin=
e,
> > +				     const struct nand_data_interface *conf) {
> > +	struct anfc_nand_controller *nfc =3D to_anfc(chip->controller);
> > +	struct anfc_nand_chip *achip =3D to_anfc_nand(chip);
> > +	int err;
> > +	const struct nand_sdr_timings *sdr;
> > +	u32 inftimeval;
> > +	bool change_sdr_clk =3D false;
> > +
> > +	if (csline =3D=3D NAND_DATA_IFACE_CHECK_ONLY)
> > +		return 0;
> > +
> > +	/*
> > +	 * If the controller is already in the same mode as flash device
> > +	 * then no need to change the timing mode again.
> > +	 */
> > +	sdr =3D nand_get_sdr_timings(conf);
> > +	if (IS_ERR(sdr))
> > +		return PTR_ERR(sdr);
> > +
> > +	if (sdr->mode < 0)
> > +		return -ENOTSUPP;
> > +
> > +	inftimeval =3D sdr->mode & 7;
> > +	if (sdr->mode >=3D 2 && sdr->mode <=3D 5)
> > +		change_sdr_clk =3D true;
> > +	/*
> > +	 * SDR timing modes 2-5 will not work for the arasan nand when
> > +	 * freq > 90 MHz, so reduce the freq in SDR modes 2-5 to < 90Mhz
>=20
> What's the freq for mode 0 and 1?
It is 100MHz in SDR mode 0 and 1.

>=20
> > +	 */
> > +	if (change_sdr_clk) {
> > +		clk_disable_unprepare(nfc->clk_sys);
> > +		err =3D clk_set_rate(nfc->clk_sys, SDR_MODE_DEFLT_FREQ);
>=20
> You should not change the clk rate here. It should be done when the chip =
is selected, so that,
> if you ever have 2 different chips connected to the same controller, you =
can adapt the rate
> when they are accessed.
Ok, got it. I will update.

>=20
> > +		if (err) {
> > +			dev_err(nfc->dev, "Can't set the clock rate\n");
> > +			return err;
> > +		}
> > +		err =3D clk_prepare_enable(nfc->clk_sys);
> > +		if (err) {
> > +			dev_err(nfc->dev, "Unable to enable sys clock.\n");
> > +			clk_disable_unprepare(nfc->clk_sys);
> > +			return err;
> > +		}
> > +	}
> > +	achip->inftimeval =3D inftimeval;
> > +
> > +	return 0;
> > +}
> > +
> > +static int anfc_nand_attach_chip(struct nand_chip *chip) {
> > +	struct mtd_info *mtd =3D nand_to_mtd(chip);
> > +	struct anfc_nand_chip *achip =3D to_anfc_nand(chip);
> > +	u32 ret;
> > +
> > +	if (mtd->writesize <=3D SZ_512)
> > +		achip->spare_caddr_cycles =3D 1;
> > +	else
> > +		achip->spare_caddr_cycles =3D 2;
> > +
> > +	chip->ecc.calc_buf =3D kmalloc(mtd->oobsize, GFP_KERNEL);
> > +	chip->ecc.code_buf =3D kmalloc(mtd->oobsize, GFP_KERNEL);
>=20
> Those bufs are allocated but never freed (memleak). Also, are you sure yo=
u really need them.
These bufs are freed in nand_release(), which is calling from anfc_remove()=
.

And chip->ecc.code_buf, is used in anfc_read_page_hwecc().
What we are doing here is, extract ECC code from OOB and place it in ecv.co=
de_buf, and passing this info to nand_check_ecc_chunk(buf, chip->ecc.size, =
&ecc_code[i], eccbytes, NULL, 0,chip->ecc.strength).
i.e. just to store ECC code from OOB area.
=20
And chip->ecc.calc_buf is no where used in the driver, I will remove it.

Thanks,
Naga Sureshkumar Relli.