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[209.132.180.67]) by mx.google.com with ESMTP id c17si18506281pfb.81.2018.12.04.06.23.05; Tue, 04 Dec 2018 06:23:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S0yHUTLL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726482AbeLDOU1 (ORCPT + 99 others); Tue, 4 Dec 2018 09:20:27 -0500 Received: from mail-ua1-f66.google.com ([209.85.222.66]:44570 "EHLO mail-ua1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726151AbeLDOU0 (ORCPT ); Tue, 4 Dec 2018 09:20:26 -0500 Received: by mail-ua1-f66.google.com with SMTP id d19so5807929uaq.11 for ; Tue, 04 Dec 2018 06:20:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=HAOz37Zy1sG6FReaAnpmdWLSFulPqs4JVrBMAsBYt6M=; b=S0yHUTLL6A6lSCr/Z9RFKauRN++8MedauuZBnkgI5e7+vfqcToToj75M3HMpH28gFf RV1hHCDYpNbwu9oIe96x03Ihws+NI1ermJ9HdJuLhnGY9XJZ8qm6OgUA+zz3Oh6Up+Km YeMwgHc8/2e2uELSwaSYt1+vzF1TpWOiIpFCE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=HAOz37Zy1sG6FReaAnpmdWLSFulPqs4JVrBMAsBYt6M=; b=Ba0hS30rHzaMKeUbkiqmInhB0A1xAF0vnQMwklxky0UscxJBCLQnVUvsddpuR4A+5n NWbdA6ub+6rDkWoTaTUxHk6J9y8GsWd4PZ+RSb+kGXK02zWWYCtKopoqplw5IIZoiOqJ +AqaptDs0UC4uYajHUF5u3hLgmMxIFUMG3qYOO/aBREZFqfKQZy0YKsx0U/vf/BIaQxZ muy+YiIWrkMCS8BwhxaEEW/mmmNY2PJ9yAjbySFhayvKz5iBF8BrTiKuUkMmHO3j8pda tGyiLes9BQzD8J2NFkw1F1cav4u+gMrkbI1ZTPydqUqECcG+gcUqPwKyuO+jxfr//xHF Jw4A== X-Gm-Message-State: AA+aEWbf1fLvOQFoWO8KPPJQo4nOMNTPtJVTu9CctVBhb0KHzH1xGFag LG7db4Dp0MAcQ3AuTWT3DVbJ+fCz+B7hwUl0aMSdGg== X-Received: by 2002:ab0:31d5:: with SMTP id e21mr9490411uan.107.1543933224364; Tue, 04 Dec 2018 06:20:24 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Ulf Hansson Date: Tue, 4 Dec 2018 15:19:48 +0100 Message-ID: Subject: Re: [PATCH v1 1/1] mmc: core: control EXT_CSD_CACHE_CTRL from device tree To: Liming Sun Cc: Jaehoon Chung , David Woods , Shawn Lin , "linux-mmc@vger.kernel.org" , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 20 Nov 2018 at 21:06, Liming Sun wrote: > > Currently the EXT_CSD_CACHE_CTRL register is controlled by API > mmc_card_broken_hpi(), which only works for the quirks settings. > This commit enhances it to use card->ext_csd.hpi instead. This > flag works for both the quirks and the broken-hpi configuration > in the device tree. > > Signed-off-by: Liming Sun I realize that the code around the HPI support needs some additional love. Let me post some patches in a day or two, then you can have a look a let me know your thoughts. > --- > drivers/mmc/core/mmc.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c > index bc1bd2c..2f2b65c 100644 > --- a/drivers/mmc/core/mmc.c > +++ b/drivers/mmc/core/mmc.c > @@ -1791,8 +1791,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, > * If cache size is higher than 0, this indicates > * the existence of cache and it can be turned on. > */ > - if (!mmc_card_broken_hpi(card) && > - card->ext_csd.cache_size > 0) { > + if (card->ext_csd.hpi && card->ext_csd.cache_size > 0) { Actually, I don't see a reason to why we should limit to use the cache, to whether HPI is supported or not. I guess the thinking behind this, was that we wanted an option to abort the cache flush as there is no timeout available for that operation. However, I don't see whenever we should allow a cache flush to be aborted, as it would introduce a potential option of getting corrupt data on the flash. > err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, > EXT_CSD_CACHE_CTRL, 1, > card->ext_csd.generic_cmd6_time); > -- > 1.8.3.1 > Kind regards Uffe