Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp8440313imu; Tue, 4 Dec 2018 08:23:41 -0800 (PST) X-Google-Smtp-Source: AFSGD/W/ROKxN2IEljbNiLy9gBbDtyQKiwPnKJ6A+IDTRtrbgGMRLX2TPGawgsqdeHs0+LuT2fgj X-Received: by 2002:a62:4156:: with SMTP id o83mr20536690pfa.72.1543940621391; Tue, 04 Dec 2018 08:23:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543940621; cv=none; d=google.com; s=arc-20160816; b=CixJHG9SKFFIl/2/BpV1lJWmtf/WZY32H/OSIaVxbU2PnLtrtuBV4we93f8+P6p65Y NOGER5/1mS7lnFKRpvHkZWm0nY/AhcWTAFHt4JufHB+5XwF2/8sKZWe50uY/FXW7bBN7 Cah+xJ7mFrBQ8/zRAtntfo/oiO2Vf1OvhPz4GiVqnGxA32L99nt1iecbfsjClw7sQqDk 3/A5GXKgSFFVEWp9S9YolsLUuTMkxJMa6Q6e5Ki3IhJrbR2anQuDZ9xsWLLzOQ0+9M/H VHHr72ikGhQhi4U0/wxKVQR3cDP4YWyfCzgQOnAeKTYzozhQkIU/TtMR7/7eVNp8EVmz 48Mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=KMlte9UNWPA7zCADlWhe+O6sUhEJK0A+qHxwy2MnBew=; b=gNfdTmv4QnEnuWIrcqSoph5xhPw5wZ/0+rKOw5G385Bl2DbTwMBOCG1Ovr9w+gUakY p0tCo1H4JJ1+SobeBzOm2/aK4Naz6TDNbtqWPz9XALsrsuHNyEQmGscb4GbIJewjCCJK HujuHHEQEC5LpPu/h9x0uxoeYx7+SsML1x4orOFOhLwimS33g4ghcy7DwxkC4+MsOdf6 UPGkVL7FGLNygDXOSeWzbmyVxH0CsxvLqZTUUQ5xzRnOXLvl2KmNVuvZEFOavwGMHb0r 710eqyiUKaRNuhK4ZfpUWT49SDc+FchGdZS02avDoIQwz6+qM2/EP3ecAXa/I1NEsz/1 hc5g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w10si14310663pgj.214.2018.12.04.08.23.25; Tue, 04 Dec 2018 08:23:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726570AbeLDQVP (ORCPT + 99 others); Tue, 4 Dec 2018 11:21:15 -0500 Received: from foss.arm.com ([217.140.101.70]:36262 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726151AbeLDQVP (ORCPT ); Tue, 4 Dec 2018 11:21:15 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 21B06A78; Tue, 4 Dec 2018 08:21:15 -0800 (PST) Received: from arrakis.emea.arm.com (arrakis.cambridge.arm.com [10.1.196.113]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 313783F614; Tue, 4 Dec 2018 08:21:13 -0800 (PST) Date: Tue, 4 Dec 2018 16:21:10 +0000 From: Catalin Marinas To: Julien Thierry Cc: linux-arm-kernel@lists.infradead.org, daniel.thompson@linaro.org, Jason Cooper , marc.zyngier@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, christoffer.dall@arm.com, james.morse@arm.com, joel@joelfernandes.org, Thomas Gleixner Subject: Re: [PATCH v6 05/24] irqchip/gic-v3: Switch to PMR masking before calling IRQ handler Message-ID: <20181204162109.GA19210@arrakis.emea.arm.com> References: <1542023835-21446-1-git-send-email-julien.thierry@arm.com> <1542023835-21446-6-git-send-email-julien.thierry@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1542023835-21446-6-git-send-email-julien.thierry@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 12, 2018 at 11:56:56AM +0000, Julien Thierry wrote: > Mask the IRQ priority through PMR and re-enable IRQs at CPU level, > allowing only higher priority interrupts to be received during interrupt > handling. > > Signed-off-by: Julien Thierry > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Thomas Gleixner > Cc: Jason Cooper > Cc: Marc Zyngier > --- > arch/arm/include/asm/arch_gicv3.h | 17 +++++++++++++++++ > arch/arm64/include/asm/arch_gicv3.h | 17 +++++++++++++++++ > drivers/irqchip/irq-gic-v3.c | 10 ++++++++++ > 3 files changed, 44 insertions(+) For the arm64 bits: Acked-by: Catalin Marinas (this time without the legal disclaimer ;))