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[209.132.180.67]) by mx.google.com with ESMTP id 41si18758701plf.347.2018.12.04.14.44.27; Tue, 04 Dec 2018 14:44:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=Ed92oC8a; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726728AbeLDWne (ORCPT + 99 others); Tue, 4 Dec 2018 17:43:34 -0500 Received: from mail-pg1-f194.google.com ([209.85.215.194]:42696 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726677AbeLDWnW (ORCPT ); Tue, 4 Dec 2018 17:43:22 -0500 Received: by mail-pg1-f194.google.com with SMTP id d72so8032872pga.9 for ; Tue, 04 Dec 2018 14:43:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9xlMXzrv29FE6wYW2xJyRjVPKQcP2QW3ahzcQIOcRU8=; b=Ed92oC8awKbmBQwnsTyr6PZlqONLnMoCUeV8Y/twwwLuUA2q9f6gVvNv0/CDx2ApDb C5ZOj+8g16kbx1pGbEeKfHyh5mo/m46C2C7EXJbLG85rPt2HNsLXF4mssUxsNEPY9Oso Rm+3sK01nQcRRtsBkc4G9qrlsTqqbJsiSzjsk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9xlMXzrv29FE6wYW2xJyRjVPKQcP2QW3ahzcQIOcRU8=; b=kVtlufalWFXObXa2pqnJJS7mtgK4gJ9gEmKL7I9tnZhkC395pEdP2GTEZvKqp/tWlR gYRZaSH/dHKyoxy0HkHgmXFq0iCHn+zBOQBwUCdtQVLP1j+E3zhRXFI2Xb9V5vDZIGwU meAn/eDe4hC+rbkMhBe+ZRZ+xrjFdAXi3RBOKMna6zJ1bsOSSSZEZY6j1VEXUMf6bSaf GqNbQStt2QQBe0Wc7Pae6q8QCmHs3t7F7Qi/Xl0fFMP9Q9uQpkP5ERVEgffb8GjNcEde RZXigTYX95qZqCZ4lPnKgDR8W2s46pdGaYAjT5fQE0pq0Jo2bsR2VB1pBR5MtdwMIv8B qtYg== X-Gm-Message-State: AA+aEWYPlXWCNmS/YWzfHcQTHIX5va2cdvTSxZppVg/aohxrn+jkw/Mg W1gtz6nf+TRdGIAIsUKvWoz0nw== X-Received: by 2002:a62:5793:: with SMTP id i19mr22153955pfj.49.1543963402277; Tue, 04 Dec 2018 14:43:22 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:b6af:f85:ed6c:ac6a]) by smtp.gmail.com with ESMTPSA id y184sm21961917pgd.71.2018.12.04.14.43.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Dec 2018 14:43:21 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Kaehlcke Subject: [PATCH v4 8/8] ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY Date: Tue, 4 Dec 2018 14:42:34 -0800 Message-Id: <20181204224234.62619-9-mka@chromium.org> X-Mailer: git-send-email 2.20.0.rc1.387.gf8505762e3-goog In-Reply-To: <20181204224234.62619-1-mka@chromium.org> References: <20181204224234.62619-1-mka@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add 'xo_board' as ref clock for the DSI PHY, it was previously hardcoded in the PLL 'driver' for the 28nm 8960 PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd --- Changes in v4: - added 'Reviewed-by: Stephen Boyd ' tag Changes in v3: - patch added to the series --- arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 48c3cf4276101..d337ae9326cd8 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1338,8 +1338,9 @@ <0x04700300 0x200>, <0x04700500 0x5c>; reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; - clock-names = "iface_clk"; - clocks = <&mmcc DSI_M_AHB_CLK>; + clock-names = "iface_clk", "ref"; + clocks = <&mmcc DSI_M_AHB_CLK>, + <&xo_board>; }; -- 2.20.0.rc1.387.gf8505762e3-goog