Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp11088572imu; Thu, 6 Dec 2018 11:19:35 -0800 (PST) X-Google-Smtp-Source: AFSGD/VRBKoQyCzFtydj2RaXxSZL17WRdv0pnNnZdzzFyNc3ahL53CbnWP06uloO9fWneSZAx3Ln X-Received: by 2002:a17:902:6bc7:: with SMTP id m7mr30079540plt.106.1544123975518; Thu, 06 Dec 2018 11:19:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544123975; cv=none; d=google.com; s=arc-20160816; b=cEXOX7RYc2KX1bmtIH0mIKDpa5aVDMUolOiK0RG23v1B0YoCDzHojiBBbAEjuA4/Tg xpXpgt3P3V8Dxc8QyBrQQoCFBK2P/Kl4fe+1vNutBO/TnTCKRp4zHKwepiyZhliy6jkB hQE9R859kYXlgeH1qlkAp9KxM0dJ/pVemcP7szYcE+vDuBDrVe0ZhLv45R98B13QAE3r fQkCIyRsEd/fOvFB54jOLLJC1dd2clxjkGIvySVjJeP19aMlDPBHU2pMg9rqFyxAfsAy Jiyw+Z0eaRQ4+2vVZtQSeWwIQQAn0zVWtcABkGlLkjzfpXPZK18khFRN1HDUdatNHBfm t1jQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-transfer-encoding:content-disposition:mime-version :references:message-id:subject:cc:to:from:date; bh=+aZ9F7pwsDKGbRIM8NVPyA+BZJynNkwdnDnXaoXBFy8=; b=nB+OrWi6MmFQfW8Fiqbd/QY+5ZA5LG0jkOMjYJmT58QIBH54xfhVb6MBLuZq0V+Pho 4O/88CbZ7MdU6gvoO5o1KHUXIBJbeYEzpW7FyN/FKs9ewve5tg9Go+a0tWCjhpftzLKT 3kSSfzfpirUu9mvXTqLhA9glomhQKxvwU+7Bemef0eCU+gmGngUiTvw5ngOZB5j3L9Nu 0sa7DMsrQkIKbw+4nGJ9acPvjHACEIbzIaeXe2lRB+K1lJv1Dys+doYOItDXZf5nZA/D B3EsAnZReDvQxZOg9CzI89OjALJiOmHCO1w4viEuRpb0mAmlZsj2SvnK0AgRGIPHS6nO 8EmA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s17si844159pgi.513.2018.12.06.11.19.20; Thu, 06 Dec 2018 11:19:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726021AbeLFTSb (ORCPT + 99 others); Thu, 6 Dec 2018 14:18:31 -0500 Received: from foss.arm.com ([217.140.101.70]:59094 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725930AbeLFTSa (ORCPT ); Thu, 6 Dec 2018 14:18:30 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 63072EBD; Thu, 6 Dec 2018 11:18:30 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 33C293F59C; Thu, 6 Dec 2018 11:18:30 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 56E061AE0BAD; Thu, 6 Dec 2018 19:18:51 +0000 (GMT) Date: Thu, 6 Dec 2018 19:18:51 +0000 From: Will Deacon To: Alexander Van Brunt Cc: Ashish Mhetre , "mark.rutland@arm.com" , "linux-tegra@vger.kernel.org" , Sachin Nikam , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH V3] arm64: Don't flush tlb while clearing the accessed bit Message-ID: <20181206191850.GC20796@arm.com> References: <1540805158-618-1-git-send-email-amhetre@nvidia.com> <20181029105515.GD14127@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Alex, Thanks for running these tests and providing the in-depth analysis. On Mon, Dec 03, 2018 at 09:20:25PM +0000, Alexander Van Brunt wrote: > >?If we roll a TLB invalidation routine without the trailing DSB, what sort of > >?performance does that get you? > > It is not as good. In some cases, it is really bad. Skipping the invalidate was > the most consistent and fast implementation. My problem with that is it's not really much different to just skipping the page table update entirely. Skipping the DSB is closer to what is done on x86, where we bound the stale entry time to the next context-switch. Given that I already queued the version without the DSB, we have the choice to either continue with that or to revert it and go back to the previous behaviour. Which would you prefer? Will