Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
MIME-Version: 1.0
References: <20181203123524.11778-1-anup@brainfault.org> <mhng-41a72f59-6506-420f-a01e-b01c81ab6e33@palmer-si-x1c4>
In-Reply-To: <mhng-41a72f59-6506-420f-a01e-b01c81ab6e33@palmer-si-x1c4>
From:   Anup Patel <anup@brainfault.org>
Date:   Fri, 7 Dec 2018 07:57:26 +0530
Message-ID: <CAAhSdy2g_-kYYrW4VJffLPA8evK9mjby06izC6FmNkRe3SceSQ@mail.gmail.com>
Subject: Re: [PATCH] clocksource: riscv_timer: Provide sched_clock
To:     Palmer Dabbelt <palmer@sifive.com>
Cc:     Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Atish Patra <atish.patra@wdc.com>,
        Christoph Hellwig <hch@infradead.org>,
        linux-riscv@lists.infradead.org,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>
Content-Type: text/plain; charset="UTF-8"
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On Fri, Dec 7, 2018 at 2:02 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Mon, 03 Dec 2018 04:35:24 PST (-0800), anup@brainfault.org wrote:
> > Currently, we don't have a sched_clock registered for RISC-V systems.
> > This means Linux time keeping will use jiffies (running at HZ) as the
> > default sched_clock.
> >
> > To avoid this, we explicity provide sched_clock using RISC-V rdtime
> > instruction (similar to riscv_timer clocksource).
> >
> > Signed-off-by: Anup Patel <anup@brainfault.org>
> > ---
> >  drivers/clocksource/riscv_timer.c | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c
> > index 084e97dc10ed..431892200a08 100644
> > --- a/drivers/clocksource/riscv_timer.c
> > +++ b/drivers/clocksource/riscv_timer.c
> > @@ -8,6 +8,7 @@
> >  #include <linux/cpu.h>
> >  #include <linux/delay.h>
> >  #include <linux/irq.h>
> > +#include <linux/sched_clock.h>
> >  #include <asm/smp.h>
> >  #include <asm/sbi.h>
> >
> > @@ -49,6 +50,11 @@ static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
> >       return get_cycles64();
> >  }
> >
> > +static u64 riscv_sched_clock(void)
> > +{
> > +     return get_cycles64();
> > +}
> > +
> >  static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {
> >       .name           = "riscv_clocksource",
> >       .rating         = 300,
> > @@ -97,6 +103,9 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> >       cs = per_cpu_ptr(&riscv_clocksource, cpuid);
> >       clocksource_register_hz(cs, riscv_timebase);
> >
> > +     sched_clock_register(riscv_sched_clock,
> > +                     BITS_PER_LONG, riscv_timebase);
>
> Shouldn't this just be 64, not BITS_PER_LONG?  We have 64-bit counters on
> RV32I.

Ahh, yes. I got mislead by "mask" field of clocksource.

I will change this to 64 and add another patch on fix "mask" of
clocksource as well.

Regards,
Anup