Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp577245imu; Fri, 7 Dec 2018 05:47:59 -0800 (PST) X-Google-Smtp-Source: AFSGD/X2mXN9nLFmNpKcNfsl18TweWYnKyy8Cpm9uc0AmuTVqK0Z28oTD2vSmMa4GDJVMPkfWVlO X-Received: by 2002:a62:9111:: with SMTP id l17mr2319995pfe.200.1544190479280; Fri, 07 Dec 2018 05:47:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544190479; cv=none; d=google.com; s=arc-20160816; b=feqQ7giCX51xq2nSlsv+Ca6C34GkJdyHzsFmjP7bcKuYpZUYcMmOHxbgyA4F5/qGhp wcs6IorFqatK44Mi04OPDiDghRfBmUaykH3pkmaMeVkpTzryZfP7A9eBQTv/IuAT3TAG dhys3ce96rDd13LAZHBfZhzsXgZNLD8XGWCWJooyNEetB+fKTmH4X+CeG4+02nTcLfVE uXbpZo19XAsYV7G7dLgMiprAUevqg9AXkL8+QPpXErKkF492OMmn71NTKbso1KVuNn4H pe7ynzkNkkr8mPyE9o8B2PEVahFHy4XjFGMC84/CPO/2Flm8JvgH0UaMmq/fpSV1K8cY dDrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=Hn+zTyaKVeCTuh/xQhWc+z0O+HCxnfW2uIVEac1nsEI=; b=EFnDMWlIiseTjrS0Y+PymN6o6gr9tgrXtZSY8tF3TE/3kEF2hCG3Jyput12LjaPXu9 xF0ZlyqcjrjmZ40eINcyiITNjGhG5IADXcMADjLv8CGDOUrxFi8AiqxVcCxrhggTBrf2 hPv+tHaSWwF6UWNKGWnSyrm5PRdenGgnsgP7N8sDp1Se/JwC4t2eMVHRkmAEbOUe9szw Ef7WbqgrYblKP2/oLHbP1c5AYPgdZyg15Vn5EgydGr44aQ4tun9m6o/EToEcvJMsb1T5 or0Qrf6kkuD/kZffOvR97ELCUBg6zcQY4r3lR2O+fkY+Zr0bRaIPthn1+SQa0sGc16r4 8LsQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j5si3139955pfg.254.2018.12.07.05.47.44; Fri, 07 Dec 2018 05:47:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726067AbeLGNpf (ORCPT + 99 others); Fri, 7 Dec 2018 08:45:35 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:44740 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726050AbeLGNpe (ORCPT ); Fri, 7 Dec 2018 08:45:34 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 33EAF15AB; Fri, 7 Dec 2018 05:45:34 -0800 (PST) Received: from e105550-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A608C3F5AF; Fri, 7 Dec 2018 05:45:30 -0800 (PST) Date: Fri, 7 Dec 2018 13:45:21 +0000 From: Morten Rasmussen To: Atish Patra Cc: linux-kernel@vger.kernel.org, Albert Ou , Anup Patel , Ard Biesheuvel , Catalin Marinas , devicetree@vger.kernel.org, Dmitriy Cherkasov , Greg Kroah-Hartman , Ingo Molnar , Jeremy Linton , Juri Lelli , "moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)" , linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , "Peter Zijlstra (Intel)" , "Rafael J. Wysocki" , Rob Herring , Sudeep Holla , Thomas Gleixner , Will Deacon Subject: Re: [RFT PATCH v1 0/4] Unify CPU topology across ARM64 & RISC-V Message-ID: <20181207134509.GA5913@e105550-lin.cambridge.arm.com> References: <1543534100-3654-1-git-send-email-atish.patra@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1543534100-3654-1-git-send-email-atish.patra@wdc.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thu, Nov 29, 2018 at 03:28:16PM -0800, Atish Patra wrote: > The cpu-map DT entry in ARM64 can describe the CPU topology in > much better way compared to other existing approaches. RISC-V can > easily adopt this binding to represent it's own CPU topology. > Thus, both cpu-map DT binding and topology parsing code can be > moved to a common location so that RISC-V or any other > architecture can leverage that. > > The relevant discussion regarding unifying cpu topology can be > found in [1]. > > arch_topology seems to be a perfect place to move the common > code. I have not introduced any functional changes in the moved > code. The only downside in this approach is that the capacity > code will be executed for RISC-V as well. But, it will exit > immediately after not able to find the appropriate DT node. If > the overhead is considered too much, we can always compile out > capacity related functions under a different config for the > architectures that do not support them. > > The patches have been tested for RISC-V and compile tested for > ARM64 & x86. The cpu-map bindings are used for arch/arm too, and so is arch_topology.c. In fact, it was introduced to allow code-sharing between arm and arm64. Applying patch three breaks arm. Moving the DT parsing to arch_topology.c we have to unify all three architectures. Be aware that arm and arm64 have some differences in how they detect cpu capacities. I think we might have to look at the split of code between arch/* and arch_topology.c again :-/ Morten